Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

NIOS II SPI Slave with FIFO

SAN
Beginner
887 Views

Hi,

I would like to receive N bytes of data using SPI(3 Wire Serial) IP in Qsys.

All N bytes are transferred by the master during one chipset toggle.

I implemented the RX interrupt, but I could see only the last byte.

(Previously received data is overwritten)

So, I think I need a FIFO that can store the received data.

But ​I do not know what to do.

Can somebody give me an advice? 

Thank You.

0 Kudos
1 Reply
Vicky1
Employee
165 Views

Hi,

Try to set the bits in control Register & then check status of the status Register.

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

Reply