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Altera_Forum
Honored Contributor I
761 Views

NIOS II Timer Interval Core Question!

Hi,  

I am trying to generate three different clock cycles; Given below is what i am trying to generate 

 

Clock1 ¯¯¯¯|_|¯|_|¯|_|¯|_|¯¯¯¯¯¯¯¯¯¯¯ Please note that clock 1 starts out high and 

 

Clock2 ______|¯|_|¯|_|¯|_|¯|_________ switches to zero where as clock 2 and clock 3 

 

Clock3 ___________________|¯|______ starts out at 0 and switches to high. High=3.3V 

 

I hope the figure is readable and understandable. All these three clocks needs to be at 7.75MHz and all must be synchronized. The frequency of these three clocks must also be easily changable. I already have this working using verilog and some PLLs. But now, i want to switch my entire design to NIOS II processor and use timer interval to generate them.  

 

Following are my questions; 

1. Is it possible to generate these three clocks using timer interval? 

2. If it is possible, will they be synchronized?  

3. How can i go about changing the clock frequency dynamically?  

 

P.S. I already read the document regarding the timer core and from my understanding of the timer core, i do believe that generating these required frequency is a piece of cake. I am just not so sure about being able to change the frequency dynamically. 

 

Question about interval timer core: 

Suppose my timer core is running at 4MHz. And my timeout period is set at 1Second. When the timeout pulse produces a pulse, when the internal counter count downs to zero, does it produce a 1Sec pulse or a 4MHz pulse? 

 

Best Regards,  

Pratish (PK)
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4 Replies
Altera_Forum
Honored Contributor I
50 Views

You might find it best to write your own timer/counter - then you'll know exactly what is happening. 

 

7.75MHz is (if my sums are correct) 129.03225ns, you aren't going to get the accuracy of a PLL from a fixed frequency counter. I don't know whether you could run a counter at 1GHz - but even that would only give options of 7.692MHz, 7.752MHz and 7.813MHz. 

 

Long term accuracy can be acheived by adding an extra count on some cycles (basically a digital PLL) - but that will give short term jitter.
Altera_Forum
Honored Contributor I
50 Views

 

--- Quote Start ---  

You might find it best to write your own timer/counter - then you'll know exactly what is happening. 

--- Quote End ---  

 

 

will writing my own timer/counter keep all three clock in sync? All three clocks being in sync is very important. Also these three clocks are just the first phase of the program. Eventually, i will need to generate 9 clocks ( 3 sets of 3 clocks) and all these three clocks will be interdependent of each other and all three clocks must be reconfigurable!
Altera_Forum
Honored Contributor I
50 Views

Could you shift register (or similar) to control each output once the main timer has expired? 

 

I'm not sure what you mean by 'in sync' - you have multiple edges at the same time - they will not happen together!
Altera_Forum
Honored Contributor I
50 Views

yes, "in sync" meaning multiple edges at the same time. But if this is not possible, then difference between them should be very minimum and easily reconfigurable. What do you think will be the best way to go for this? PLL? timer? or counter?

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