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12435 Discussions

NIOS II access via avalon-mm to PCIe registers

Honored Contributor II

I want to develop a PCI express rootport to control an endpoint PCIe card. I have used a Avalon-MM Cylone V Hard IP for PCI Express to design the rootport and a NIOS II processor to develop the driver. The problem is that I can't access to PCIe register as CRA and TXS that are interconnected to NIOS II processor with a avalon-mm interconnect bus. 


After the creation of the bsp I have a system.h that only includes CRA base and TXS base addresses but doesn't include anything related with internal registers. 




* pcie_cv_hip_avmm_0_Cra configuration 



#define alt_module_class_pcie_cv_hip_avmm_0_cra altera_pcie_cv_hip_avmm 

#define pcie_cv_hip_avmm_0_cra_base 0x20000 

#define pcie_cv_hip_avmm_0_cra_irq 3 

#define pcie_cv_hip_avmm_0_cra_irq_interrupt_controller_id 0 

#define pcie_cv_hip_avmm_0_cra_name "/dev/pcie_cv_hip_avmm_0_cra" 

#define pcie_cv_hip_avmm_0_cra_span 16384 

#define pcie_cv_hip_avmm_0_cra_type "altera_pcie_cv_hip_avmm" 




* pcie_cv_hip_avmm_0_Txs configuration 



#define alt_module_class_pcie_cv_hip_avmm_0_txs altera_pcie_cv_hip_avmm 

#define pcie_cv_hip_avmm_0_txs_base 0x20000000 

#define pcie_cv_hip_avmm_0_txs_irq -1 

#define pcie_cv_hip_avmm_0_txs_irq_interrupt_controller_id -1 

#define pcie_cv_hip_avmm_0_txs_name "/dev/pcie_cv_hip_avmm_0_txs" 

#define pcie_cv_hip_avmm_0_txs_span 536870912 

#define pcie_cv_hip_avmm_0_txs_type "altera_pcie_cv_hip_avmm" 


For example to access other embedded ip peripherals via NIOS II(such UARTs, PIO...), system.h includes several define for access individual registers.  



Actually I am trying to send TLP packets via reg0, reg1 and control registers directly via memory mapping: 


volatile int * rp_reg0 = (int *) pcie_cv_hip_avmm_0_cra_base + rp_tx_reg0 ; 

volatile int * rp_reg1 = (int *) pcie_cv_hip_avmm_0_cra_base + rp_tx_reg1 ; 

volatile int * rp_ctrl = (int *) pcie_cv_hip_avmm_0_cra_base + rp_tx_cntrl ; 


/* 1.Write the first 32 bits of the TX TLP to RP_TX_REG0.2. Write the next 32 bits of the TX TLP to RP_TX_REG1. 

3. Write the RP_TX_CNTRL.SOP to 1’b1 to push the first two dwords of the TLP into the Root Port TX FIFO*/ 


*(rp_reg0) = tlp_cfg_dw0(tlp_fmttype_cfgrd0); 

*(rp_reg1) = tlp_cfg_dw1( ((0 << 8) | altrpcierp_devfn), tlp_read_tag); 

*(rp_ctrl) = rp_tx_sop; 




Any idea about accessing via avalon-mm to PCIe rootport registers?. 

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