NIOS II based MultiProcessor System Design Examples

[Altera_Forum]

Dear All, 

 I was just wondering if anyone has the older design examples of 'NIOS II Processor Based MultiProcessor System Design' including their hardware and software project files?   I'm NOT looking for the 'Dining Philosophers' design example which is already available on Altera's website but the previous ones which I didn't find on Altera's website. Waiting for your kind response.

[Altera_Forum]

Hi, 

 Refer below link which gives detailed steps to create system MultiProcessor for an example.  https://www.altera.com/en_us/pdfs/literature/tt/tt_nios2_multiprocessor_tutorial.pdf  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

--- Quote Start ---  Hi,  Refer below link which gives detailed steps to create system MultiProcessor for an example.  https://www.altera.com/en_us/pdfs/literature/tt/tt_nios2_multiprocessor_tutorial.pdf  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)  --- Quote End ---    Dear Anand,  I'm not looking for this 'Dining Philosopher' example whose link you provided as I have gone through it already. I want the older ones with hardware and software project files for reference. I don't know how to make multiprocessors communicate with each other using shared memory. If you can help me in this regard then please reply at your earliest convenience.  Regards, Rizwan Fazal

[Altera_Forum]

Hi, 

 Refer below link for the reference design. http://www.alterawiki.com/uploads/6/6b/multi-core_nios_ii_processors_reference_design_based_on_arria_10_soc_development_board.pdf  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[beyondTime]

Hello,

maybe a 2010 research study "Design and implementation of embedded multiprocessor architecture using FPGA"

 https://www.researchgate.net/publication/261127288_Design_and_implementation_of_embedded_multiprocessor_architecture_using_FPGA

suites your interest or additionally the yet not mentioned

chapter "8. Hardware Acceleration and Coprocessing"

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/edh_ed51006.pdf

documentation from Altera.

Best regards, beyondTime