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I create system design based on NIOS II/s core (insrt cahe 512 bytes).
In my design programm and data memory located in SRAM (Cyc. dev board). RESET and ISR code in on_chip RAM. My program work correctly (instr. cashe not used). When I replace NIOS II/s to NIOS II/f core my programm start work incorrectly (not work lwip stack). What reason for this behavior?Link Copied
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The are two potential reasons why your Nios II/f fails.
There is a known bug in the Nios II/f data cache in release 1.0 that shows up on Cyclone. A fix for this bug will be released in a few weeks with the Nios II 1.0.1 release. The bug is a rare case that only shows up in unoptimized code. So, as a quick experiment, make sure all your code is compiled with optimization enabled. The other possibility is that the data cache isn't being bypassed/flushed consistently by the software. The Nios II/f uses a writeback cache so if software bypasses the data cache on a store and then uses a normal load that reads the value from the data cache, the most-recent value of that address won't be returned. This is not a bug in the data cache but is a bug in the software. Can you tell me more about your SOPC Builder system and the software you are running?- Mark as New
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//------------------------------------------------------
Quartus design: VHDL full_featured System libtrary: 1C20_full (altera full_featured design), single thread Design compiler: Quartus 4.1 SP1 Fitter settings: Physical synthesis effort: NORMAL Perform physical synthesis for combinational logic = checked Perform register duplication = cheked Perform register retiming = cheked Application: catted stand alone lwIP WEB server (removed all application calls), lwipopts.h by default. Test task: checking PING function //------------------------------------------------------ Test options: Linker: all memory place to ext_ram. Optimization(NONE): lib: -O0 app: -O0 Data cashe: 2KByte - passed Data cashe: 1KByte - failed ( printf ("Application started.\n"); executed. ) 1KByte(Set compiler options for lib & app to: -O3, -faster code) - failed. 1KByte(as prev., rwdata placed to SDRAM) - failed. //------------------------------------------------------ In the main code data cashe memory dirrectly not used!!!int main(void)
{
struct netif netif;
struct ip_addr ipaddr, netmask, gw;
unsigned int now, lasttime;
int i;# if IP_REASSEMBLY
int j;# endif
alt_avalon_lan91c111_if* dev_list_ptr = (alt_avalon_lan91c111_if*)alt_ethernet_device_list.next;
printf("Example web server using Light-weight IP (LWIP)\n");
printf("and simple RAM-based file system.\n\n");
/* Initialize lwip */
lwip_init();
printf ("Setting IP address to: %d.%d.%d.%d\n", IPADDR0, IPADDR1, IPADDR2, IPADDR3);
printf ("Setting netmask to: %d.%d.%d.%d\n", NETMASK0, NETMASK1, NETMASK2, NETMASK3);
printf ("Setting gateway address to: %d.%d.%d.%d\n", GWADDR0, GWADDR1, GWADDR2, GWADDR3);
IP4_ADDR(&ipaddr, IPADDR0, IPADDR1, IPADDR2, IPADDR3);
IP4_ADDR(&netmask, NETMASK0, NETMASK1, NETMASK2, NETMASK3);
IP4_ADDR(&gw, GWADDR0, GWADDR1, GWADDR2, GWADDR3);
netif_add(&netif, &ipaddr, &netmask, &gw,
(void*)dev_list_ptr,
lan91c111if_init,
ip_input);
netif_set_default(&netif);
/*Initialize application(s) */
/*
* main loop to service the Ethernet device and expire TCP timers
*/
printf ("Application started.\n");
lasttime = get_milliseconds();
i=0;# if IP_REASSEMBLY
j=0;# endif
while(1)
{
lan91c111if_service(&netif);
now = get_milliseconds();
if (now - lasttime > TCP_TMR_INTERVAL) {
lasttime = now;
tcp_tmr();
if (++i==50) { /*etharp_tmr();*/ i=0; }
}
# if IP_REASSEMBLY
if (++j==1000) { ip_reass_timer(); j=0; } # endif
}
}
Any comments?
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Don't forget to make things like this:
alt_avalon_lan91c111_if* dev_list_ptr = (alt_avalon_lan91c111_if*)alt_ethernet_device_list.next; volatile declerations (volatile doesn't bypass cache anymore, but it should be done still since the compiler could synthesize that out).
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