Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12409 Discussions

NIOS II outputs and Metastability

Altera_Forum
Honored Contributor II
1,400 Views

Hi folks, 

 

Is it safe to assume that the outputs from an embedded NIOS II can be used in other areas of the FPGA logic without worrying about metastability. In the case in question, The NIOS and logic are both being driven from the same PLL, but using different taps. The logic is at 400MHz and the NIOS at 100MHz. 

 

Will I be free of metastability issues? My immediate assumption would be yes but that is an assumption. 

 

Many thanks 

deBoogle
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
69 Views

 

--- Quote Start ---  

Hi folks, 

 

Is it safe to assume that the outputs from an embedded NIOS II can be used in other areas of the FPGA logic without worrying about metastability. In the case in question, The NIOS and logic are both being driven from the same PLL, but using different taps. The logic is at 400MHz and the NIOS at 100MHz. 

 

Will I be free of metastability issues? My immediate assumption would be yes but that is an assumption. 

 

Many thanks 

deBoogle 

--- Quote End ---  

 

 

You need follow same rules of clock domain transfers. In this case if fpga clock is 4*nios clock and are in phase then the two clocks will always be related in same way so you don't need resync of logic and timequest will report if any violation occurs across.
Altera_Forum
Honored Contributor II
69 Views

Cheers Kaz, that is what I suspected. 

D
Reply