Nios® V/II Embedded Design Suite (EDS)
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NIOS II reset

Altera_Forum
Honored Contributor II
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Hi, 

 

I am connecting the board reset to the NIOS II reset input in the qsys design. The reset vector address is set to the onchip memory. I use the eclipse tool to download my software application. On board reset I see that the application does not execute again. I will have to download the application again to get it working whereas there is no need to program the .sof file on reset. What is the reset requirement of the NIOS II processor. How can I fix this issue. 

 

Thanks & Regards 

Bhavya K
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7 Replies
Altera_Forum
Honored Contributor II
362 Views

Is the same board reset connected to the onchip memory as well?

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Altera_Forum
Honored Contributor II
362 Views

Hi, 

 

Yes the same reset is used for the onchip memory as well.
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Altera_Forum
Honored Contributor II
362 Views

Can you attach your Qsys system?

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Altera_Forum
Honored Contributor II
362 Views

It is quite a big system now, so there are many things in the qsys system. You can have a look

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Altera_Forum
Honored Contributor II
362 Views

Also you will need to connect the jtag_debug_module_reset to all Nios peripherals including onchip-memory.

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Altera_Forum
Honored Contributor II
362 Views

So you mean to say everything controlled by NIOS should have the jtag_debug_module_reset connected to it?

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Altera_Forum
Honored Contributor II
362 Views

Yes. It is recommended to connect the same reset sources to Nios and its peripheral to ensure that they get reset at the same time.

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