NIOS II soft reset

[Altera_Forum]

Hi i am new to the NIOS II features. I am working on a cyclone V (5CEFA4U19C7) which has a Nios II processor in it. I want to do a soft reset which is, resetting the NIOS without power cycling it. I did the watchdog timer , but I have a doubt in it as to whether the resetrequest signal should be tied to the reset input of the timer block(a pic is attached). Also how do I test the soft reset, coz the document says that the system will reset when the software stops executing normally, how to get this feature to work so that i can test whether the soft reset is working or not. 

 Please guide me through this problem.  Thanks, Sid

[Altera_Forum]

Refer to chapter 28 - "Interval Timer Core" of the "embedded peripherals ip user guide (https://www.altera.com/literature/ug/ug_embedded_ip.pdf)". This explains, pretty well, this IP and using it as a watchdog. 

 Critically, it states "to prevent an indefinite resetrequest pulse, you are required to connect the resetrequest signal back to the reset input of the timer." So, yes. You're doing the right thing.  As for a 'soft' reset - this is a soft reset. Simplistically, a reset that doesn't rely on an external hardware event (e.g. power cycle, reset button) is a soft reset. So, providing your Nios restarts when the watchdog goes off, you've proved your soft reset works.  Cheers, Alex

[Altera_Forum]

Hey Alex, 

 Thanks for clarifying my doubt. I also have another doubt in this. In the document it tells that the system will reset if it stops working properly, how do I test this feature? Also it tells that I have to periodically write some value in one of the period registers to prevent resetting, does this mean I have to write a piece of code to do this or the block automatically does it. I am a bit confused by this explanation.  Thanks, Sid

[Altera_Forum]

The idea of a watchdog is that the software interacts with it (writes something to it) every so often (periodically) from the software, to prove the processor and software is running. If the write doesn't occur, due to the processor stopping, the WD triggers a reset. 

 So, yes you need some code, but if you're using Nios you'll have some code. Assuming you have a main loop in your code, simply insert a write to the appropriate WD register to 'kick' the watchdog. Providing the loop runs your WD will be kicked. There may be some restrictions on how quickly you write to it. Check the docs. There will be a maximum time within which you must write to it.  Testing such a feature opens quite a philosophical debate. You'll have to do something predictable to test a function that's there to detect an unpredictable event.  Simplest suggestion is, once you get it working, remove the line of code that kicks the WD and prove that the processor sits there continually resetting.  Cheers, Alex