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Altera_Forum
Honored Contributor I
1,076 Views

NIOS + Pipeline Bridge

How can someone make memory imported through an MM pipeline bridge visible in Eclipse/NIOS? 

On BSP editor I can only see the on-chip memory.  

I'd like to place .rwdata .rodata on that section upon load. 

Thank you!
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10 Replies
Altera_Forum
Honored Contributor I
59 Views

One way you can try is by creating virtual memory via the nios2-bsp-editor at the linker script tab. The virtual memory should contain the information of the pipeline bridge, ie base address/size.

Altera_Forum
Honored Contributor I
59 Views

Hit "Add Memory Device", put the name of the component "mm_bridge".  

But then in Problems I see "Memory Device mm_bridge is not visible in the SOPC design" 

I saw another post here where someone solves it by setting the property "isMemoryDevice" in a .tcl file.  

I suppose this is the nios_hw.tcl file that you export from qsys? But looking into this file there is no "isMemoryDevice" property anywhere. 

Please advise?
Altera_Forum
Honored Contributor I
59 Views

I think you can ignore the error. Once you add memory device, you can proceed with the "Add" button. It should work. Just select the mm_bridge as the memory device. You can assign the linker region to the mm_bridge once you do that. 

 

I think you need to look for the pipeline_bridge_hw.tcl. Should be located by right-click on the IP in Qsys, go to details>> open component directory. You should see the hw.tcl and just add the property. Not too sure about the syntax though.
Altera_Forum
Honored Contributor I
59 Views

Nopes. Cannot ignore the error.  

If you actually ignore, there will be two sections with the same name, one with the "memory" attribute and the other without. 

If you just add a memory region on top of the memory section, you wont be able to put any linker section on it because the pulldown boxes will not have it. 

If you add a new memory device with another name, HAL even compiles OK but the actual project fails in compilation time with a crazy offset error out of boundaries.  

 

I finally got it done by adding the "isDeviceMemory" to "1" in the module "mm_bridge", interface "s0" in the nios.socpinfo file. It is a PITA to find the right location. XML is unreadable. 

I'm sure this will get reset next time I regenerate the HDL files.  

Wonder if there is any other way. Wish there was a button in GUI somewhere to make this easier.
Altera_Forum
Honored Contributor I
59 Views

If you modify the sopcinfo, it will be overwritten every time you re-generate the Qsys file. You need to update at the pipeline_bridge_hw.tcl. Or another way is to make a copy of the pipeline_bridge folder can find somewhere in your $QUARTUS_INSTALL/ip/altera/merlin/altera_avalon_mm_bridge to your Qsys directory and then modify the hw.tcl.

Altera_Forum
Honored Contributor I
59 Views

In the file that @mikedsouze mentions, you need to add the following line at the end: 

 

set_interface_assignment s0 embeddedsw.configuration.affectsTransactionsOnMasters {m0} 

 

What this will do is instruct Eclipse to look beyond the pipeline bridge and map any memory devices which are on the other side.
Altera_Forum
Honored Contributor I
59 Views

I'm not sure what's the role of the .tcl file if I add it to the project though. Is it going to be automatically rerun every time I kick in a new recompile?  

Or if I re-export the qsys file as tcl again, will this line be overwritten?
Altera_Forum
Honored Contributor I
59 Views

The tcl file is for Qsys, you don't add it to your project. When Qsys adds the component it parses the tcl file to understand what it should look like. When you generate the HDL for Qsys it once again parses the tcl file to work out which files it needs and how to make the connections, as well as instructions on how to make the .sopcinfo file (e.g. embeddedsw assignments).

Altera_Forum
Honored Contributor I
59 Views

Oh so it's a different .tcl file. I'm referring to the TCL file you create through "File... export hardware as tcl". Is that the same? 

Then the qsys project is loaded up in top/verilog. Does this tcl file get parsed again in this specific case?
Altera_Forum
Honored Contributor I
59 Views

When you export a system as a TCL file, any components used in it remain separate. When the HDL is generated all of the TCL files required for the system are parsed and a .sopcinfo file is generated for everything. So if you add the line into the pipeline_bridge_hw.tcl file as suggested, then regenerate the HDL (you don't need to re export the system as a TCL, just regenerate the HDL), then the command should be in the .sopcinfo file and Eclipse should see your memory.

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