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Altera_Forum
Honored Contributor I
1,335 Views

NIOS can not boot from EPCS ?!!!

Hi guys , im trying to make the NIOS II boot from the same EPCS where the configuration is stored.  

Im using Quartus 13 and it has only the legacy serial flash controller. The documentation says the first 1-Kbyte of the address space of the flash controller is a ROM bootloader . So I set the value of the reset vector to the address of the serial flash controller , and the reset offset to 0x00000000 (pointing to the bootloader) and the exception vector pointing to On-chip RAM . I then converted the .SOF of the FPGA and the .elf file of the NIOS app to flash files using the following commands:  

sof2flash --input=hw.sof --output=hw.flash --epcs --verbose 

elf2flash --input=sw.elf --output=sw.flash --epcs --after=hw.flash –verbose 

nios2-elf-objcopy --input-target srec --output-target ihex sw.flash sw.hex 

then I followed the following method to program the EPCS using Altera USB blaster: 1. Open the Convert Programming File tool from the file menu in Quartus II 

2. Select .jic file for “Programming file type” 

3. Select EPCQ256 for “Configuration device” 

4. Make sure “Active Serial” is selected for “Configuring device mode”. 

5. Click on “Flash Loader”, then click on “Add Device” to select the Cyclone V device you’re using then click “Ok”. 

6. Click on “SOF Data”, then click on “Add File” to select the .sof file generated by Quartus II compilation. 

7. Click on the .sof file you have just added, click on “Properties” and enable the “Compression” 

Page 3 of 4 

8. Click the “Add Hex Data” button 

9. Select “Relative Addressing” 

10. Select your <project>.hex file containing your Nios II software image 

11. Click on “Generate” to generate the .jic file 

I then re-power , the FPGA configuration works , but the NIOS is not booting as it should (Whole design working on 25 MHz) 

Now whats the problem ?
0 Kudos
11 Replies
Altera_Forum
Honored Contributor I
170 Views

Hi Muhammad, 

 

1.Have you tried by loading sof and run as hardware? does it work.?(to check the design part) 

2.Try to load .jic for simple program like hello world project. (to check the hardware part) 

3.Are you using development board  

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
170 Views

Yes , the hardware works , it just a simple blinking LED program . I downloaded it to OCRAM through JTAG n let the NIOS boot from there , and its working fine . Now I want to make the NIOS boot from the external EPCS.  

And yes Im using a development board from third party supplier.
Altera_Forum
Honored Contributor I
170 Views

Hi  

 

Is there any default program in epcs device?can you see default program running?  

OR 

Can you try to load .pof with help of flash loader. 

Which board you are using(part number& family)? 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
170 Views

I can see the FPGA configuration working , as I see LEDs turned on , but the NIOS application is not running.  

I'm using Cyclone III (EP3C16G240) .  

One thing I noticed during Quartus compilation is a warning that the external flash memory pins (used as general IOs) are stuck to Vcc or Gnd .  

Could that be the problem ? How while they are connected to the EPCS serial flash controller?  

I hope there is some clear demo for this , as I can not find one.
Altera_Forum
Honored Contributor I
170 Views

Have you constrained your EPCS pins? FPGA boot doesn't rely on this but Nios application boot will. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
170 Views

PROBLEM SOLVED .  

I was using a NIOS II-e instance , and booting from EPCS was only supported by NIOSII-f .
Altera_Forum
Honored Contributor I
170 Views

Hello everyone, 

 

I am facing similar problem. I have a NIOS II E based system and I created the .jic file and loaded into EPCQ64 and booted the system without any problem. Now I changed NIOS II E to NIOSE II F as I need faster processing. I compiled the project and it works fine and even imporved. But when i genereate the hex file for NIOS II F version and so the .jic and download it to EPCQ64, the system doesnt boot up ?  

 

As I said, it works fine and boots up with NIOS II E and NOT with NIOS II F. Any idea suggestion ?
Altera_Forum
Honored Contributor I
170 Views

 

--- Quote Start ---  

Hello everyone, 

 

I am facing similar problem. I have a NIOS II E based system and I created the .jic file and loaded into EPCQ64 and booted the system without any problem. Now I changed NIOS II E to NIOSE II F as I need faster processing. I compiled the project and it works fine and even imporved. But when i genereate the hex file for NIOS II F version and so the .jic and download it to EPCQ64, the system doesnt boot up ?  

 

As I said, it works fine and boots up with NIOS II E and NOT with NIOS II F. Any idea suggestion ? 

--- Quote End ---  

 

 

Can some one help me as I am still unable to resolve the issue ?
Altera_Forum
Honored Contributor I
170 Views

Please note it is EPCS64 and NOT EPCQ64

Altera_Forum
Honored Contributor I
170 Views

Problem fixed by increasing the Exception vector offset address.

Ganesh
Beginner
162 Views

---------
Problem fixed by increasing the Exception vector offset address.

--------

 

Hi,

I am also facing the same problem. I have NIOS II Faster Processor in my desing and using Quartus 14.1. When sof is loaded directly on FPGA then it works fine (LED blinks in logic and Hello world printed from application) but, when I am trying to load it form EPCS flash memory then FPGA Boots (LED blinks) but NIOS II does not(No Hello wolrd printed). I have bought IPS-Embedded License and using Cyclone IV E FPGA.

I have set Reset Vector to base address of EPCS Controller(0x1008_0000) with offset to 0x0000_0000 and exception vector to OCM base address(0x0002_0020) with offset to 0x0000_0020 (this offset is automatically generated).

Here the question is, are these two offesets correct?

For programming, I first convert .sof and .elf to .flash files and then .flash files to .hex files. After that I generate .jic file using .hex files.

One thing I am not sure about is, do we have to include .qip file (generated in mem_init process) in .sof file. I tried both way i.e. with and without .qip file but it does not work.

Please help, its been last whole week I am trying to reach solution.

 

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