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Altera_Forum
Honored Contributor I
1,201 Views

NIOS executes main() function repeatedly without use of any finite/ infinite loop

Have a very nice day everyone. 

This is my ever first post and I am new to working on HDLs/ qsys/ and NIOS eclipse. 

I can not figure out why NIOS should execute the main() function repeatedly with even few simple statements like below: 

int main(){ 

printf("1 - - Hello world\n"); 

printf("2 - - Hello world\n"); 

printf("3 - - Hello world\n"); 

return 0; 

 

The output for this is: 

1 - - Hello world 

2 - - Hello world 

3 - - Hello world 

1 - - Hello world 

2 - - Hello world 

3 - - Hello world 

1 - - Hello world 

2 - - Hello world 

3 - - Hello world 

1 - - Hello world 

2 - - Hello world 

3 - - Hello world 

continued ... without any stop. 

However you may see there is no any loop statement being used. 

 

Hardware details: 

My system is basically a video capture project using Stratix IV (DE-4 board). 

I am using onChipMemory for NIOS instruction and data, DDR3 for buffering of live captured video and works well. 

All the controllers used in qsys are connected with afi_clk output of DDR3, where memory clock frequency is 200MHz and achieved local clock frequency is 100MHz. 

All set of PIOs including buttons, switches and LEDs are connected to 10MHz received from PLL. Due to different clcok domains, I used Clock bridge also connecting Master with 10MHz (PLL) and Slave with 100MHz (afi_clk). DDR3 and PLL both receive external clock of 50MHz. 

 

Any further information may be asked. I cannot figure out why my NIOS is triggered repeatedly to execute above code. 

Thanks in advance
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4 Replies
Altera_Forum
Honored Contributor I
31 Views

Hi, 

 

1.What happens when to assert reset(Nios II /qsys system) monitor the reset signal using signal tap? 

2.Are you loading the write file? 

And share the images of reset signal if possible  

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
31 Views

Thanks a lot sir Anand 

Here I am attaching qsys filtering the clk and rst connections. 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=14780  

 

I cannot understand why the system is giving this problem. Actually it is not looping rather it is executing/ entering the main () repeatedly. Your point is worth understanding, NIOS may be is resetting and therefore re-executing the main function. But I cannot figure out where it is lacking. 

 

Thanks
Altera_Forum
Honored Contributor I
31 Views

Hi, 

 

Have you solved the problem? 

Can you design simple project for hello world from below link and check? 

If it works you can compare the design 

 

https://www.altera.com/en_us/pdfs/literature/tt/tt_my_first_nios_sw.pdf 

https://www.youtube.com/watch?v=1a_cd6fbroa 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
31 Views

hi Anand - Thank you so much for my problem followup. 

 

Sir, I was connecting both master and slave clocks of Clock bridge with CLK50 i.e. external clock which was generating problems. 

I solved it by connecting m0_clk to afi_clk output of DDR while s0_clk is left with external clock, and it works fine now. 

 

Now I am facing another problem BUT closely related to the same issue. 

I want read the contents of DDR from Base Address using IORD function in NIOS Eclipse using C, 

It can easily read data in Hex upto 1KB (1024 bytes), 2KB, 3KB also but beyond that if I keep for example MemSize for reading 4096 or say 8192 bytes etc,  

it stops reading upto approx 3806 (not exactly but approx) bytes then it simply loops out. I am worried why I cannot read data as much I like. 

I need to read image data from memory which is 100s of KBytes but my system runs out after less than 4KB access. 

 

I must add here that there is no problem in C program or subroutine accessing the memory, as same set of C instructions are working perfect to read as much data from memory 

using software of Altera Sample Project DE4_230_DDR2_UniPHY_14.0 which is simply using DDR, PIOs buttons and LEDs along with necessary controller IPs.  

 

While my Project is similar with added Terasic camera IP and related controller for video capture and then PIOs for SD card interface also 

(Kindly refer to QSYS snapshot I posted in last reply) 

 

Do I need use separate clock bridges for PIOS (buttons , LEDs and Switches) and PIOS specially used for CLK, DAT, CMD and WE ports for SD card??