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Altera_Forum
Honored Contributor I
757 Views

NIOS flash programmer question.

Hello all, 

 

I'm having trouble understanding the EPCS flash controller. I use Quartus-II / NIOS version 8.1 build 163. I need to stay at 

this version because of legacy systems. 

 

- I have a previous design using a Stratix-II with an EPCS64. I successfully have it copying the EPCS64 image into local SRAM 

and run both FPGA configuration and NIOS software [using the uCOS-II OS]. No problems, the mechanism works just fine. 

 

- My newer design uses a Stratix-III with a EPCS64. When I try and use the NIOS flash programmer to do the same, it complains 

that my input file is too big. In Quartus-II, the configuration scheme is 'active serial' and device is set for EPCS64 [as it is with 

the Stratix-II FPGA]. I've also tried to make the FPGA configuration and NIOS application smaller, but with the same results. 

 

Is there anything different that I should consider or settings when using these different FPGA's ?  

 

Please advise, thank you in advance.
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3 Replies
Altera_Forum
Honored Contributor I
22 Views

Is compression enable for the sof image?

Altera_Forum
Honored Contributor I
22 Views

Thank you for your reply, sorry for my delayed response. 

 

Under Settings->Device->Device and Pin Options->Configuration, the 'Generate compressed bitstreams' is checked. Is this what you mean ? 

 

Thanks again,
Altera_Forum
Honored Contributor I
22 Views

As I recall there is also an option for compressing the sof in the flash programmer GUI.