NIOS is constantly reading from instruction memory and reading/writing to data memory

[Altera_Forum]

Hello all, 

 I am still working on my first NIOS design and am having troubles with the instruction/data memory access. Below is a schematic of the NIOS and its peripherals. The NIOS is connected to a ROM for instruction memory, and a RAM for data memory. The data memory is also connected to an Avalon bridge in order to communicate with an external RTL component.   http://www.alteraforum.com/forum/attachment.php?attachmentid=10670&stc=1   When I do an RTL simulation of this design, I see very random reads and writes to data memory and continuous reads from the instruction memory. Regardless of what is included in my .s source file, I see this behavior. Can anyone explain to me why I am seeing this? Shouldn't I be expecting instructions reads based off the instructions in my assembly file?  http://www.alteraforum.com/forum/attachment.php?attachmentid=10671&stc=1

[Altera_Forum]

Unless you have a HALT instruction in your ram, I would expect to see continuous reads from the instruction memory. Unless your NIOS has instruction cache and it's enabled,

[Altera_Forum]

If this is your first NIOS design, I highly recommend that you build the design in Qsys. Start with an online lab that can get you started. Try this class: http://wl.altera.com/education/training/courses/oniihw - there is lab that takes step by step on how to build up a Qsys system with a NIOS and peripherals and then you can compile Hello World SW. Then expand from there. Best of luck!

[Altera_Forum]

--- Quote Start ---  Unless you have a HALT instruction in your ram, I would expect to see continuous reads from the instruction memory. Unless your NIOS has instruction cache and it's enabled,  --- Quote End ---    At the end of my assembly file, I did not branch to main, or any other label. In doing so, I assume the program halted at the last instruction used. From what I have been able to find, there is no NIOS halt instruction.

[Altera_Forum]

--- Quote Start ---  If this is your first NIOS design, I highly recommend that you build the design in Qsys. Start with an online lab that can get you started. Try this class: http://wl.altera.com/education/training/courses/oniihw - there is lab that takes step by step on how to build up a Qsys system with a NIOS and peripherals and then you can compile Hello World SW. Then expand from there. Best of luck!  --- Quote End ---    I have gone through a few different tutorials. I seem to have everything setup in qsys. I believe my problem is coming from the eclipse software build tools. I have not found a whole lot of information there.

[Altera_Forum]

Eclipse error messaging sometimes isn't clear. First make sure that it reads the .sopcinfo file that correlates to your design. Then if things don't seem to behave, make the onchip code storage memory as large as you can and trim later. If you run out of code space, Eclipse isn't that clear about telling you so. Add a JTAG UART to your setup that you show in your schematic and try the hello_world_small template might be a good place to start.

[Altera_Forum]

--- Quote Start ---  Eclipse error messaging sometimes isn't clear. First make sure that it reads the .sopcinfo file that correlates to your design. Then if things don't seem to behave, make the onchip code storage memory as large as you can and trim later. If you run out of code space, Eclipse isn't that clear about telling you so. Add a JTAG UART to your setup that you show in your schematic and try the hello_world_small template might be a good place to start.  --- Quote End ---    Eclipse read my .sopc info file. When I compiled my source code as well, it was successful. I tried both .c and .s and I got successful compilation. All I am attempting to do in the source code is to write to the Avalon bridge in order to initiate an Avalon write transaction to my external RTL component that the nios will connect to. Even though the code was correct (writing to the base address of the avalon bridge) I would not see a write transaction on my Avalon master. I would also see all those random, and invalid read and write transactions on the onchip data and instruction memory. Most of the had the data 0xDEADBEEF, so I am assuming something is going wrong, I just cant seem to find it!  Thanks

[Altera_Forum]

There is no instruction that could stop a Nios. Nios will always fetch instructions from its instruction memory and it is not instruction dependent at all.  

 I am concern that the data_bridge will not work since it is exported as nios_mm. From your diagram, is it true that data master is connected to data_mem and data_bridge only? I would advice to move your custom component into the Qsys and either connect that directly to Nios data master or connect it to the data_bridge.  Let me try to explain.  Bridges in Qsys is transparent to Nios. Nios master interfaces (instruction/data masters) see through bridges. Therefore, once you exported the m0 interface of the bridges just like what you are doing with the data_bridge, Nios sees nothing at all and will ignore the bridge. What happen here is that Nios will not be able to address whatever that is at the bridge.  If you open your sopcinfo, look for dataSlaveMapParam, under the value column you should see all the connected slave to the data master. I bet you will just see the data_mem.  If you want to workaround this, you can try to add a dummy component in Qsys, such as another memory and place them in this order: 1. data_mem 0x0_0000 - 0x0_ffff 2. data_bridge 0x1_0000 - 0x1_ffff 3. dummy_ram 0x2_0000 - 0x2_ffff  This would allow the effective addressable range of the data master to be from 0x0 to 0x2_ffff. Else without the dummy ram the data master can address only between 0x0 - 0xffff (as in the dataSlaveMapParam), which will ignore your data bridge. Do note that the addresses are just for references. You do not need to follow them, but the order is important.  Hope this helps.