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Altera_Forum
Honored Contributor I
1,332 Views

NIOS2 on De2 board - verification failed

Hello! 

 

I'm new to NIOS system programing. I am trying to make simple program based on my altera DE2 board with cyclone 2 ep2c35f672c6n on board. 

 

#include <stdio.h> #include "system.h" #include "alt_types.h" #include"altera_avalon_pio_regs.h" int main(void) { unsignedchar pom; unsignedchar dygacz=1; int i=0; while(1) { pom=IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE); { for(i=0;i<1000*pom;i++); dygacz=dygacz<<1; if(dygacz==0) dygacz=1; IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE,dygacz); } }; return 0; }  

 

As i follow the instructions/tutorials/how to-s im getting to the point of programing the board, however im getting an error message, followed by error popup saying: "downloading elf process failed" 

Using cable "USB-Blaster ", device 1, instance 0x00 Pausing target processor: OK Reading System ID at address 0x01001020: verified Initializing CPU cache (if present) OK Downloading 00800000 ( 0%) Downloaded 19KB in 0.3s (63.3KB/s) Verifying 00800000 ( 0%) Verify failed between address 0x800000 and 0x804943 Leaving target processor paused  

 

 

After some diging in the Internet, i'v found how to disable verification. I did it by changing line in nios2-download file  

 

From eval nios2-gdb-server $arglist 

 

To eval nios2-gdb-server --no-verify $arglist 

 

 

 

 

 

 

 

 

right now, im not getting any error popups and the console log looks like this: 

 

Using cable "USB-Blaster ", device 1, instance 0x00 Pausing target processor: OK Reading System ID at address 0x01001020: verified Initializing CPU cache (if present) OK Downloading 00800000 ( 0%) Downloaded 19KB in 0.3s (63.3KB/s) Starting processor at address 0x008001C4  

 

 

 

everything looks just fine, with one exception - there is nothing happening on DE2 board! Moreover if the NIOS CPU "entry" point is at 008000000 why is it starting from 0x008001C4?? 

 

 

 

The funny part in all of this, that me and my firend have found the workaround for this. It is strange, but it proofs, that SRAM on board is programmed properly. The workaround is three simple steps (however we need two computers for this): 

 

 

 

 

1) Program DE2 board with Quartus 9.1 SP1 on computer one 

 

2) Then RUN nios application from eclipse (run as nios hardware) 

 

----- NOW THE FUNNY PART------ 

3) Get your error message, than unplug JTAG usb cable from your computer, plug it to my friend's computer and PROGRAM DE2 BOARD WITH THE SAME SCHEMATIC THAS U DID IN STEP 1 

--- VOILA!---  

The NIOS2 app, that u loaded in step 2 works fine now.  

For those, who didn't understand me due to my low language skills, we have prepared a VIDEO showing everything we are doing. 

 

 

 

 

 

 

 

 

PLEASE someone tell me, how to run this fricki'n thing on one computer only. 

 

 

 

www youtube com/watch?v=1HUt3KEVLik 

Replace spaces with . 

 

 

PS. SOOOORRRYYY EVERYONE FOR MY BAAAD ENGLISH :)
0 Kudos
11 Replies
Altera_Forum
Honored Contributor I
65 Views

Hello  

I have a file in the host computer "C:\" and I went to open it from NIOS II IDE, but the function fopen() don't work, please can something HELP ME !!!!! please
Altera_Forum
Honored Contributor I
65 Views

What are your processor reset and exception addresses? You find them in system.h file and they must be the same as defined in Nios properties in SOPC builder.

Altera_Forum
Honored Contributor I
65 Views

 

--- Quote Start ---  

Moreover if the NIOS CPU "entry" point is at 008000000 why is it starting from 0x008001C4?? 

--- Quote End ---  

 

 

The reset address contains a jump instruction to the start of the program. The function alt_main() starts at address 0x008001C4 and can change with each compile.
Altera_Forum
Honored Contributor I
65 Views

@Jab - U are propably right, but still its not up to the programmer to interpret jump directives, so still as for me, it should be the entry point (offset 0x0)  

 

@Cris72 

SDram base address is 0x0800000 

NIOS CPU reset offset is 0x0 

Interrupt vector offset is 0x20 

 

in system.h the same values 

# define NIOS2_BIG_ENDIAN 0 #define NIOS2_BREAK_ADDR 0x1000820 #define NIOS2_CPU_FREQ 50000000u #define NIOS2_CPU_ID_SIZE 1 #define NIOS2_CPU_ID_VALUE 0x0 #define NIOS2_CPU_IMPLEMENTATION "tiny" #define NIOS2_DATA_ADDR_WIDTH 25 #define NIOS2_DCACHE_LINE_SIZE 0 #define NIOS2_DCACHE_LINE_SIZE_LOG2 0 #define NIOS2_DCACHE_SIZE 0 #define NIOS2_EXCEPTION_ADDR 0x800020 #define NIOS2_FLUSHDA_SUPPORTED #define NIOS2_HARDWARE_DIVIDE_PRESENT 0 #define NIOS2_HARDWARE_MULTIPLY_PRESENT 0 #define NIOS2_HARDWARE_MULX_PRESENT 0 #define NIOS2_HAS_DEBUG_CORE 1 #define NIOS2_HAS_DEBUG_STUB #define NIOS2_HAS_JMPI_INSTRUCTION #define NIOS2_ICACHE_LINE_SIZE 0 #define NIOS2_ICACHE_LINE_SIZE_LOG2 0 #define NIOS2_ICACHE_SIZE 0 #define NIOS2_INST_ADDR_WIDTH 25 #define NIOS2_RESET_ADDR 0x800000 # define SDRAM_0_BASE 0x800000  

Altera_Forum
Honored Contributor I
65 Views

I succeded to create it, we must disable "small C library" and "light API" and i could write on it, but when i try get character from it, i couldn't because i haven't enough memory on chip, so i added SDRAM 

My problem is how to use SDRAM because each time i have this message error: 

 

/****** 

Verifying 00800000 ( 0%) 

Verify failed between address 0x800000 and 0x8038BB 

Leaving target processor paused 

/******* 

 

please can someone HELP ME please !!!!!!! please please please please please please please please please
Altera_Forum
Honored Contributor I
65 Views

You probably have a timing problem on the SDRAM. Try with a design that already has the SDRAM component, such as one of the kit's example designs.

Altera_Forum
Honored Contributor I
65 Views

think you for your information but can you please give give me the exact file, i search it but i found only file in verilog or VHDL but didn't find Block file .bdf!!! please HELP!!!

Altera_Forum
Honored Contributor I
65 Views

I don't have a DE2 so I can't check it, but in the kit example designs you should have one with a name such as nios-standard. It should include a properly configured SDRAM controller.

Altera_Forum
Honored Contributor I
65 Views

OK!! my probleme is : I went to take data from file .txt in the host computer and display it on LCD but when i used fopen et fgetc, there is a message which told me taht my memory on chip is full, so i must add sdram or sram and boot from it, please have you any idea how to do it??

Altera_Forum
Honored Contributor I
65 Views

The nios standard design example given with the kit probably has everything you need to do that.

Altera_Forum
Honored Contributor I
65 Views

Your problem may be related to the SDRAM may be related to the use of the PLL. 

It seems you must use a second un-skewed clock for the nios 2. 

i found this info on a site for a Cornell grad course - ECE 5760  

Advanced Microcontroller Design 

and system-on-chip  

Fall 2011. 

 

Look at the GCC examples page for the info. 

Replace the Nios2 clk_50 input with the second? c1 output of the ALTPLL. 

I called the wire CPU_CLK. 

 

Now you can increase you program size with or without micrium or linux.