I was a little curious to know how much performance a core synthesized at an FPGA chip could achieve if compared to a commercial off the shelf core designed directly on ASIC, but I got surprised to see that according to Table 2 of document bellow...https://www.altera.com/products/processors/overview.html ...the NIOSII processor shows similar performance if compared to the ARM Cortex-M1. Ok, I´m aware that such comparison at first sight shouldn´t matter due both are different cores, whose design surely was optimized to fit respectively at each standard cells or logic cells, and I´m also aware that there are a lot of other factors which impacts on the performance of each one, as amount of layers stacked and size of theirs manufacturing process technology, but I´m also assuming that both were designed to achieve the best performance possible. Even considering the reasoning above, souldn´t have the ASIC design a much better performance if compared to a FPGA based design, or I´m missing some point ? ( I´m guessing that the flexibility of an FPGA must have a cost in the design, that not only the greater size compared to an ASIC ).
Although not specifically mentioned on the page, the ARM Cortex M1 was specifically targeted for FPGA's and the speeds they state are in line with the FPGA performance:http://www.arm.com/products/processors/cortex-m/cortex-m1.php The MIPS/MHz at the same process node is a question. At a 65 NM node you can probably run an M1 hardcore much faster than the 200 MHz listed. But at the same time you can run the M1 in a Cyclone III device at 100 MHz, which will be much better than an M0 or M0+ running at 50 MHz which is probably on a 130 nm process. NIOS has process features that cover the range, and is a trade off of size vs performance, but is a decent processor. That being said however, you will pay more for a soft core NIOS if it' bumps your FPGA size up that just adding an external CPU. The SOC chips are really nice if they fit your need, but if you are looking at a M0, the dual A9's are overkill and probably bump you into a much bigger FPGA as well. Pete
hi anakha,I know that the cost per die size in a FPGA is much higher than if compared to an ASIC design, but I was really focusing only on the performance aspect. I was considering non usual application where the multicore ability of the NIOSII would make difference, and there are no commercial options available. Thanks a lot for reply.