I am working to develop PCIe Driver on X86 Linux System for Cycleon V FPGA System.I have included DMA Read/Write Control in FPGA System as well. Now, I want to use standard DMA Read/Write Operations to send/receive data. Does any one has idea or any reference link to develop Linux Driver for DMA Transfer? Regards, Ritesh Prajapati
--- Quote Start --- I am working to develop PCIe Driver on X86 Linux System for Cycleon V FPGA System. I have included DMA Read/Write Control in FPGA System as well. Now, I want to use standard DMA Read/Write Operations to send/receive data. Does any one has idea or any reference link to develop Linux Driver for DMA Transfer? Regards, Ritesh Prajapati --- Quote End --- Does any one has idea about how to develop DMA based driver under linux system? Regards, Ritesh Prajapati
I don't think there is any way to get an x86 system to initiate PCIe dma transfers.So any dma transfers would have to be generated by the fpga. The simple dma controller won't generate suitable Avalon cycles, the scatter gather one will, but it is serious overkill (beware of the default sizes of its internal fifos). Back to back write transfers from the x86 cpu actually seem reasonably fast, reads are another matter. I suspect the fpga is delaying the pcie 'ack' that the cpu needs in order execute any more instructions for 128 clocks (of the 62.5MHz app clock). There are similar delays (somewhere) when the fpga is the pcie master. Get the x86 cpu to do slave accesses to the fpga and the dma transfers speed up by a factor of 2!
Hi DSL,Thanks for Reply. Can I directly map DMA TXS Slave Controller to any of BAR Regions from FPGA Design and use that buffer directly as DMA Read/Write Transfer functionality from X86 System? Is it possible or feasible way to do in FPGA and Linux X86 System to access DMA Buffer directly from X86 System? Regards, Ritesh Prajapati
There is nothing to stop you programming an on-fpga dma controller over pcie.You'll need to find a suitable dma controller, I wrote one for our system (I'm a software engineer, I know a little vhdl and it wasn't hard).
Hi DSL,Currently, I have suggested my FPGA Engineer to implement DMA Controller into FPGA Design and assign that TXS Slave DMA Interface to one of BAR Region. So that, I can directly access that region to read/write data through DMA Interface from Linux X86 System. Please share your idea or information if you have better way to implement it. Regrads, Ritesh Prajapati
Should work.The DMA engine needs to do correctly sized avalon burst cycles into the pcie avalon slave. I did pipelined avalon reads from the internal memory block. Didn't bother overlaping the reads and writes - allowed a simple 64-bit wide memory block be used ho hold the data. I dual ported that memory block to the avalon bus and used it to hold the addresses, length, sttaus (etc). Gave me a multi-channel dma controller (round robin, doing one burst per channel) for not much resource use.
Hi DSL,So, You have assigned your DMA control to one of your internal memory section which is in any BAR Region in your FPGA Design and you are accessing data through read/write operation from that memory region through DMA Interface. Please let me know if i am wrong. Regards, Ritesh Prajapati
Hi DSL,Also one morething that do I need to configure or write any internal PCie IP Core Register to access DMA Interface from Linux X86 System through PCIe Interface? Please let me know if you have any idea for that. Regards, Ritesh Prajapati
Hi DSL,I am giving brief description about what i want to do in Cycleon V FPGA Board which is connected in Linux X86 System through PCIe Interface. I have assigned one custom controller in FPGA design which has some control registers, write master and read master. Now, I have configured only BAR 0 region in my system in which i have assigned one test register, on chip memory and control regusters of custom controller. Now, I have assigned start address of both master read & write component of my custom controller to one of section in BAR 0 region. Is it possible to read/write data directly through control registers by mapping read/write BAR 0 section into my Linux X86 System? Please let me know if you have any idea for that. Regards, Ritesh Prajapati
Read what I wrote yesterday into a very similar thread.Look at /sys/devices/pci* there is a standard dev entry that maps each bar. lspci will help you find your device. There are 'remore' and 'rescan' entries that give you a reasonable chance of reloading the fpga without having to reboot.