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Altera_Forum
Honored Contributor I
746 Views

Newbie regarding NIOS - can I mix VHDL with NIOS in Cyclone III

Hello, 

I've been using Altera CPLDs and FPGAs strictly with VHDL code. I just learned about NIOS options for the chips. If I implement a NIOS processor in my Cyclone III, can I still run independent VHDL hardware implementations at the same time in the same chip? 

 

If so, are there tutorials or examples of how to run both at the same time? 

Thanks, 

Chris
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4 Replies
Altera_Forum
Honored Contributor I
26 Views

if you have enough resources you can run Nios processor(s) and "user logic" (VHDL code) 

 

you could approach the design in a number of ways. the easiest would be to instantiate an SOPC Builder/Qsys system into your VHDL code. the simplest way to interface a Nios to VHDL code would be a parallel I/O component 

 

you could also design your VHDL with Avalon Memory Mapped and Streaming interfaces, and populate them within SOPC Builder/Qsys and interface directly with the Nios II processor
Altera_Forum
Honored Contributor I
26 Views

Thanks for the info. I suspected that both could run in the same chip, but I didn't want to move ahead with this solution only to find that I'd gone down the wrong path. Sounds like I've got a lot of reading ahead of me.

Altera_Forum
Honored Contributor I
26 Views

Just to be sure, you describe solutions where the NIOS processor interfaces with the "discrete" VHDL implementations. Can the VHDL code perform its intended hardware tasks independent of the NIOS processor and its actions?

Altera_Forum
Honored Contributor I
26 Views

 

--- Quote Start ---  

Just to be sure, you describe solutions where the NIOS processor interfaces with the "discrete" VHDL implementations. Can the VHDL code perform its intended hardware tasks independent of the NIOS processor and its actions? 

--- Quote End ---  

Yes. 

 

For example, you can have an SOPC system defined by the top-level design file sopc_system.vhd and then completely independent logic in independent.vhd, and then put both components in a top_level.vhd file, with no signals going between them, and the two systems are completely independent. The two systems can share clock and reset. 

 

Of course, once you have a processor in the system, and it communicates with the outside world, then connecting control and status bits between sopc_system.vhd and independent.vhd can be very convenient. 

 

Cheers, 

Dave