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matrixrv
Beginner
282 Views

: Is for Avalon bus an Intel IP an formal equivalent with AXI Master from Xilinx ?

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3 Replies
Kenny_Tan
Moderator
273 Views

Avalon bus spec is different than AXI in xilinx. However, you can still make connect in btw them. The qsys will add synchronizer towards it.


Kenny_Tan
Moderator
260 Views

We do not receive any response from you to the previous answer that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


matrixrv
Beginner
256 Views

My target point is why AXI Master have no external data port.The Axi master can control read data cycle on AXI bus , write data Cycle on Axi bus , can control through its signal HOLD,HOLDA bus acces of certain slave.For any other data path - like a FTDI 8 bits data path ,it provide no connection.

Let say a 8 bits data path from FTDI RS232.we need a UART slave on AXI bus. 

Let say an another 32 bits data path an PCI bus.need an slave PCI.It mean that for any non AXI data path need a slave for that.

In Avalon architecture suppose this is the same.

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