Nios 2 Camera interface

[Altera_Forum]

Hello All, 

 I am interfacing OV2640 camera to nios2 design on De2 115. I have a custom parallel port component which is connected to 8 data lines of camera. There are 3 control signals VSYNC, HREF and PCLK. I am supposed to latch the data into memory during each PCLK period. I was thinking may be it will be a better idea to get this thing going on in hardware (May be a hardware triggered DMA?) or something rather than trying to read the port on each PCLK in software. Can anyone give some recommendation please?   Thanks so much! Best regards,

[Altera_Forum]

You could use the SGDMA in the stream-to-memory mode. Just format your incoming signal as an Avalon Stream interface.

[Altera_Forum]

In addition to what Daixiwen suggested, if you're eventually going to end up wanting to do something non-software based with the image stream, you may want to format your Avalon-ST according to the Avalon-ST Video Protocol (http://www.altera.com/literature/ug/ug_vip.pdf). 

 I'm not sure, but you might be able to get away with using the Clocked Video Input block from that suite of IP.

[Altera_Forum]

Thanks so much Ted and Daixiwen! 

 I appreciate your help.   I apologize for my ignorance, but I dont know how to make the signals as Avalon Stream interface. Right now, I have it on 8 lines of parallel port (JP5 expansion interface). What should I do to it? Please let me know.   Once I get that, then , Clocked Video Input block seems interesting,. I will study that.  Thanks again!

[Altera_Forum]

You will find the Avalon Stream specification in this document: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf 

Basically you will just need to define your 8-bits as the data signal, and add a 'valid' signal that is asserted on each clock cycle that has a new valid data signal. If your interface doesn't support backpressure, just define a 'ready' input on your Avalon interface that you ignore. If on your incoming interface you have no 'valid' signal but have new valid data on each incoming clock cycle then you can just set valid to 1 on the Avalon side. And in that case I'd strongly suggest to run the SGDMA on a faster clock rate than your incoming signal, and put a dual clock FIFO between the DMA and your video input to cross the clock domain.