Hello,We intend to use Arria V for both: ARM and Nios. I would like to ask if the following link is relevant as a guideline for using both ARM and Nios II: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/tt/tt_nios2_multiprocesso... It seems that the above link is intended for multiprocessor of Nios II only, so I'm not sure if it is relevant for ARM with Nios II. Thank you for any feedback on this issue, Ran
Well, it kind of depends on what you're trying to do. In general, there are interfaces that connect the ARM core and the FPGA side (where the Nios II is located) so if the extent of your multiprocessing is that you want to send data from one device to the other, then you have some options. Probably the easiest way to do it would be to just have a single off-chip or on-chip memory that is shared between the two processors (one can write, other can read, and vice-versa). Beyond that, a lot of the same concepts discussed in that paper are still applicable, the only difference is that instead of connecting together two Nios processors, you're connecting a Nios and an ARM core (through one of three buses: HPS-To-FPGA, LWHPS-To-FPGA, or FPGA-To-HPS). Anything that involves just instantiating something inside of Qsys to handle the multi-system interaction should work fine.