Nios AvalonMM clock crossing bridge writes only 8 bits

[Altera_Forum]

Hi, 

 I have a Nios II with the data master port (32 bit) connected to a Avalon-MM Clock Crossing Bridge to the CRA port of the PCIe core (in a Cyclone V), in Qsys.  When I'm looking at the buses in signals tap, I can see the Nios generating the writes into the bridge, but only 8 bits seems to be transferred out of the bridge into the other clock domain. I have the parameters of the bridge set with a "Data Width" of 32, "Symbol Width" of 8, and the address units set as "symbols". But all I seem to be able to write across the bus is the most significant byte, but this is copied across all 32 bits. For example, if I write 0x12345678 from the Nios, the bridge will output 0x12121212 !! (I perform the writes by by using the memory window in the Eclipse debugger, if that makes any difference !!)  I've obviously got something configured incorrectly in Qsys, but, i can't find what it is ! :oops:

[Altera_Forum]

That might be doing four separate 1-byte transfers and you slave isn't looking at the byte enables.

[Altera_Forum]

Ah, yes. It seems that the IDE (Elcipse) doesn't generate a full 32 bit write on the Avalon bus, but generates 4 writes for each byte using the byte enables, when you manually change a value in the memory window. 

Thanks !