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Altera_Forum
Honored Contributor I
792 Views

Nios Custom Component with sfixed type output

I'm writing a custom component for my nios II processor using fixed point library. 

When i import my vhdl files (also library files) in the new component wizard in qsys, it seems to not recognize the input/output ports that are sfixed type but only the std_logic or std_logic_vector input/output ports. 

Is there a way to add the fixed point library to the default qsys library or another solution?
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5 Replies
Altera_Forum
Honored Contributor I
35 Views

you could just convert your IOs to std_logic(_vector). There is the to_slv function in the fixed package.

Altera_Forum
Honored Contributor I
35 Views

thanks for your reply but i need to link my custom component to another vhdl unit outside Qsys with sfixed inputs so i need a component inside qsys with a sfixed outputs

Altera_Forum
Honored Contributor I
35 Views

That doesnt make sense. you do not NEED sfixed inputs or outputs. Its easy just to convert to SLV and then convert back in another unit. From what you said, does that mean you're using it in 2 different places?

Altera_Forum
Honored Contributor I
35 Views

 

--- Quote Start ---  

That doesnt make sense. you do not NEED sfixed inputs or outputs. Its easy just to convert to SLV and then convert back in another unit. From what you said, does that mean you're using it in 2 different places? 

--- Quote End ---  

 

 

While it's easy to convert fixed to a vector, it is not so easy to convert it back unless you make assumptions about the range of the fixed type. 

 

Kevin Jennings
Altera_Forum
Honored Contributor I
35 Views

 

--- Quote Start ---  

I'm writing a custom component for my nios II processor using fixed point library. 

When i import my vhdl files (also library files) in the new component wizard in qsys, it seems to not recognize the input/output ports that are sfixed type but only the std_logic or std_logic_vector input/output ports. 

Is there a way to add the fixed point library to the default qsys library or another solution? 

--- Quote End ---  

 

At what point is Qsys not recognizing the ports? When it is analyzing the HDL files? If so, I'm not having any difficulty having it analyze the code posted below. The three files that are included are Fixed_pkg_c.vhdl and math_utility_pkg.vhdl and Junk4.vhd, where Junk4.vhd contains the code listed below. 

 

I'm not quite sure what you mean when you say "import my vhdl files (also library files)" but then ask "Is there a way to add the fixed point library". In any case, to get through analysis you simply need to add the source code for the fixed point library to the list-o-files for Qsys to analyze for your component. 

 

If you're talking about the sfixed type not being recognized at some other point, then at what point are you talking? 

 

Kevin Jennings 

 

-- Start of Junk4.vhd -- 

library ieee; 

use ieee.std_logic_1164.all; 

library ieee_proposed; 

use ieee_proposed.fixed_pkg.all; 

use ieee_proposed.math_utility_pkg.all; 

entity foo_component is port 

Gazinta: in sfixed(2 downto -3); 

Gazouta: out sfixed(3 downto -3) 

); 

end foo_component; 

architecture RTL of foo_component is 

begin 

Gazouta <= Gazinta + 1; 

end RTL; 

-- End of Junk4.vhd --
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