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Altera_Forum
Honored Contributor I
2,204 Views

Nios II Building Error

I got this error when building a Nios II project. Please help me fix it. :) 

 

alt_sys_init.c:(.text+0x8): warning: Error: Interrupt not connected for JTAG_UART. You have selected the interrupt driven version of the ALTERA Avalon JTAG UART driver, but the interrupt is not connected for this device. You can select a polled mode driver by checking the 'small driver' option in the HAL configuration window, or by using the -DALTERA_AVALON_JTAG_UART_SMALL preprocessor flag. alt_sys_init.c:(.text+0x8): undefined reference to `__alt_invalid' collect2: ld returned 1 exit status make: *** Error 1
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21 Replies
Altera_Forum
Honored Contributor I
252 Views

As the error message suggests, either configure the BSP to use the small drivers so that you don't use interrupts, or go back to SOPC Builder / QSys and connect the JTAG Uart's interrupt port to the Nios CPU.

Altera_Forum
Honored Contributor I
252 Views

Thanks Daixiwen. Now I get this error: :rolleyes: 

 

Connected system timestamp not found on target at expected base address.
Altera_Forum
Honored Contributor I
252 Views

It looks like the FPGA configuration you have doesn't correspond to the SOPC definition that the BSP used to compile the software. Be sure that you have the right configuration. 

You can follow those steps each time you modify the SOPC project:[list][*]save SOPC project and generate it[*]compile the hardware project in Quartus[*]open the Nios IDE, check that it's pointing to the right .sopcinfo file[*]compile the software project[*]upload the correct .sof file to the FPGA (careful! if you are using IP cores without their license, the file could be a *_time_limited.sof instead of the regular one)[*]upload the software[/list]
Altera_Forum
Honored Contributor I
252 Views

I just got this warning in Quartus: 

Critical Warning: Timing requirements not met  

 

and error in Nios II: 

Verify failed between address 0x1100020 and 0x1100177 

 

:confused:
Altera_Forum
Honored Contributor I
252 Views

For the riming warning you need to open Timequest and find out the top failing paths to determine what to do. 

For the second error, first check that your main memory is indeed at address 0x1100000, and then try to run a memory test on it. But you should fix the timing problem first.
Altera_Forum
Honored Contributor I
252 Views

I checked the sram in qsys, it was indeed at address 0x01000000 to 0x011fffff. 

In TimeQuest, I found this, but I didn't know what to do: 

 

Clock ______________ Slack __________ End Point TNS 

clk_________________-1.224___________-1.596 

pll|sd1|pll7|clk[0] ____ 2.057___________0.000 

ssram_clk____________4.926___________0.000 

tck_________________18.366__________0.000 

altera_reserved_tck___45.114__________0.000 

 

:D
Altera_Forum
Honored Contributor I
252 Views

There is another report in Timequest that is called "Top Failing Paths". Is will probably be somewhere in the setup summary. Just look up for categories that are in red.

Altera_Forum
Honored Contributor I
252 Views

Here is the Top Failing Paths. What should I do? :confused: 

 

http://img715.imageshack.us/img715/6291/timequest.png
Altera_Forum
Honored Contributor I
252 Views

I find it strange that you have two different clocks on those paths... Could you describe your clock distribution, and share your sdc constraints files?

Altera_Forum
Honored Contributor I
252 Views

There is a PLL with 1 input clock and 2 output clock. I attached the sdc file. Please have a look. :)

Altera_Forum
Honored Contributor I
252 Views

From a quick look it seems that your problem comes from the fact that you defined some of the I/O in the "clk" domain when those signals are generated from a different clock in the system, that has a different frequency. You should define all your I/O delays for the flash and SRAM I/O relative to the ssram_clk clock.

Altera_Forum
Honored Contributor I
252 Views

I fixed all the failing paths, but Nios II failed to verify sram. :D

Altera_Forum
Honored Contributor I
252 Views

Now you should run a memory test. 

Are you sure your I/O timing constraints for the SRAM pins match the memory datasheet?
Altera_Forum
Honored Contributor I
252 Views

The memory test software also failed to verify sram. This is the first time I constraint the sram, but I think I do it correctly. I can send the project if you want to have a look. :D

Altera_Forum
Honored Contributor I
252 Views

Without the hardware it will be difficult to debug the project... Which test is failing exactly? Do you have any error message?

Altera_Forum
Honored Contributor I
252 Views

Hello World Small and Memory Test Small both gave this error:  

 

Using cable "USB-Blaster ", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK Downloaded 8KB in 0.1s Verifying 01200020 ( 0%) Verify failed between address 0x1200020 and 0x1201DAF Leaving target processor paused 

 

Address 0x1200020 to 0x1201DAF was sram location. :D
Altera_Forum
Honored Contributor I
252 Views

To do a memory test of SRAM you really want to load the test program to internal memory.

Altera_Forum
Honored Contributor I
252 Views

Can you tell me specificly how to load program to internal memory? :)

Altera_Forum
Honored Contributor I
252 Views

First you need an onchip memory in your system, connected to both the Nios CPU's instruction and data masters. Then in the BSP settings, set all the memory configurations to your on-chip memory. If the memory is small, select the small C option, and enable the compiler optimisations.

Altera_Forum
Honored Contributor I
90 Views

Thank you for your guide. I successfully loaded the software to FPGA, and I got flash memory test failed: 

-Data bus test failed at bit 0x1 

 

And the sram memory test made the software crashed at this point: 

-Data bus test passed -Address bus test passed -Byte and half-word access test passed -Testing each bit in memory device. 

 

I don't know how to fix. :p
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