Hi , i have a little Algorithm written for my NIOS II . And it works . I recently tested it. Now i want to implement this algorithm on my FPGA with system Verilog and also compare the speed. So first i translated my C code into system verilog. Now i want to put in some data , like "123" and see what the algorithm does. But i need a Interface. For example in my NIOSII code. I could send from the NIOSII some data like "123" and print the answer on the Console. I would be happy if anyone has a idea :D
I also made a little picture . I hope it isnt that complicated.
I am working with Quartus Prime Lite Edition
Can you try to use Intel High Level Synthesis Compiler to compile the C programming code and generate the Verilog file.
The document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-getting-start... shows the tutorial for compile the example C code and generate the Verilog file.
For more information about Intel HLS, you can look at the document as below:
hi , thank you for your answer ! yes it would be good to see how the hls converts my C Algorithm into Verilog. But i also translated it by myself. Maybe not totaly correct. So this tool will help me a lot ! But i think i also need to implement my Verilog code with the Component Editor or something else. Because i want both , my NIosII with the C algorithm and my Verilog Harwdware on the FPGA in parallel. For testing i will input something first into my NiosII code and measure the time. After this i send data to my Algorithm Hardware and also measure the time . then i can compare the time. So no big thing i think.
But i want to do it this week :P
maybe someone else has an idea.