Nios II DMA speed

[Altera_Forum]

I ran "memtest", "full featured" design on Altera/Microtronix C12 Eval. kit and got SDRAM to SDRAM DMA transfer speed of 13 MB/s. Since this was DMA in and DMA out SDRAM, I believe the speed of DMA in or DMA out SDRAM will be about 26 MB/s which is far below the maximum speed of SDRAM.  

Is there anyway to speed up SDRAM DMA speed? Thanks

[Altera_Forum]

Yes is true  

I have the same problem  with the same 13 mb/s without DMA and 30 mb/s with DMA speed   In modelisim i saw that burst mode is not working   I did't try yet arbitration of DMA  You can try increse arbitratrion of DMA and maybe it helps set dma arbitration to 8 or 16  If you use quatrus4.2 and niosv1.1 you can do it but in last version in not working  because SOPC have bugs with it. If you get burst mode let me know, please.

[Altera_Forum]

To AlexS: 

     Now I also want to see the time to study the avlon bus .But I don't how to use the modelsim to  simulate the *.c file running in the niosII.Can you help me ?       Thank you!

[Altera_Forum]

yahoo2003, 

 because the SDRAM controller keeps only one row open at a time, you won't see anything like full bandwidth when DMA'ing from and to SDRAM (unless you happen to be reading and writing the same open row). If you do a DMA transfer from an onchip memory to SDRAM, or from SDRAM to onchip memory, you should get much better performance (approaching one transfer per clock).  Increasing the arbitration priorities of the DMA masters, as AlexS suggests, may also help, but once the arbitration priority exceeds the depth of the DMA's internal FIFO you won't get any more benefit. Let me know if you want to pursue this strategy, and I'll look up the ptf assignment which specifies the FIFO depth.