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Nios II IDE STDOUT error

Altera_Forum
Honored Contributor II
1,605 Views

I created a project in Quartus that uses SRAM for Nios processor memory, and reading /writing to SDRAM. I have used this project for 2 months now, I compiled the project by accident not changing a thing now I can't use it in Nios IDE. 

 

Error message is:  

"The expected Stdout device name does not match the selected target byte stream device name." 

 

I tried just creating the project from scratch using SDRAM/SRAM for Nios Processor memory, but every time it is the same error. This is just to run a hello world. The project I was working on I was using for my senior design and only have a week until my project is due. I spent hours re-0creating my project in quartus and nios over and over again but the same error.
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3 Replies
Altera_Forum
Honored Contributor II
558 Views

1. Go into BSP editor 

2. Double check the setting for STDOUT 

3. Rebuild everything
Altera_Forum
Honored Contributor II
558 Views

 

--- Quote Start ---  

1. Go into BSP editor 

2. Double check the setting for STDOUT 

3. Rebuild everything 

--- Quote End ---  

 

 

This is what I have been doing this whole day, and again just now after reading your post and it worked. Connections were fine, re-generated bsp, rebuilt my project and it worked. 

 

On a side note, is there something I could be doing wrong where I do the same thing over and over again for hours yielding the same results until eventually things work? For example, the problem I had today. When I first ran into this first thing I did was re-generate the bsp and updated my project. Then updated quartus, and then start over from scratch. Following the same steps each time. It seems like whenever I try to create an SOPC I end up doing it repeatedly for what seems like hours. Continue with this for hours. My steps are exactly the same, I've taken screenshots and recorded myself performing the necessary steps.
Altera_Forum
Honored Contributor II
558 Views

1. I usually check image on FPGA against Nios IDE expected 

2. Double check STD settings because UART can be a STDOUT too 

3. Reprogram the FPGA configuration device
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