Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12455 Discussions

Nios II: Is there a way to control mapping of low-level resources to MLABs?

Honored Contributor II

Hi Fellow Forumers, 


I'm up against the limit of available M20K RAM blocks in a design and desperately fighting to regain blocks wherever I can. In the .fit report, I note that my Nios designs (I have multiple per design) are using M20Ks when an MLAB would seemingly be perfectly acceptable. 


For example, in my design, I see ... 



  • Register Bank A is a 32-deep by 32-wide (32x32) RAM, currently assigned to 1 M20K. 

  • Register Bank B is a 32-deep by 32-wide (32x32) RAM, currently assigned to 1 M20K. 

  • D-cache victim memory is a 8-deep by 32-wide (8x32) RAM, currently assigned to 1 M20K. 

  • D-cache tag memory is a 64-deep by 6-wide (64x6) RAM, currently assigned to 1 M20K. This is less attractive in MLAB, but still not too bad. 



In the .fit report, all of these RAM functions are set to AUTO in the Nios II Qsys module. Quartus assigns these to M20K although the .fit report says that each "Fits in an MLAB." 


Is there a way (Quartus options, Verilog directives, magic incantations) to selectively direct Quartus to use MLABs instead of M20Ks? I know how to do this for my Verilog code but these specific functions are buried deep within the Nios II module. 


Thank you in advance for any help you can provide.
0 Kudos
0 Replies