Nios II Qsys issues - Merlin Address Router

[Altera_Forum]

Hi all, 

I just wanted to post regarding the issues I had when migrating from SOPC Builder to Qsys. First I've had minor issues with compilation, but if you read AN 632, you should have no problems, up to a certain point...  The certain point is a custom designed peripheral that we have in the system, which is seen as a memory device and is used as an interface to a custom DDR memory controller. I guess this might happen with all custom memory devices, this is the reason I'm writing this post.  First of all, we have 27 bits of address, +2 bits generated by the SOPC for byte addressing, which equals to 29 bits. We don't have the use of a complete memory space, so I specified an explicit address span to 16 megabytes. Also there is no device in the system with larger address space, so technically the full address space of our system is exactly 29 bits.  However, it seems that when I generate the system, Merlin address routers are generated with full 29 bits of address space, effectively ignoring the explicit address span. In turn, this has several consequences - Merlin Address routers are generated with the maximum addressable space as 29 bits (hex: 2^0x20000000 - 1 byte addresses), while channel for our custom peripheral has 2^0x20000000 byte locations as addresses (technically, larger by +1 than the complete address space (?!?) ). This causes errors in compilation, and the only solution is to manually override values for PADx variables (inside nios_addr_router.sv files; these variables represent the "size" of the channel) to the value of the explicit address span that you have specified in your *_hw.tcl file for your custom peripheral (well, actually to the exponent of 2 which equals to your specified value for ExplicitAddressSpan Avalon property). Also, the address spaces for different channels were overlapping, so this would make more problems later, even if, somehow, the compilation succeeds.  Otherwise, I've got several Verilog errors regarding bad signal lengths. Something like: "...part-select direction is opposite from prefix index direction..." And I couldn't compile the design.  Hope someone finds this helpful... Best regards to all!

[Altera_Forum]

Can you file a service request with your design at this location: http://www.altera.com/mysupport 

 This will help ensure that this issue is resolved ASAP.

[Altera_Forum]

Service request filed! Thanks! I hope they'll work a bit harder next time - Qsys is falling apart...