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Altera_Forum
Honored Contributor I
1,115 Views

Nios II, Reset Vector : SDRAM => ok, EPCS => failed

Good morning all, 

 

I have a little problem with the nios II. 

 

In my design I use an external SDRAM, I used it as Reset Vector and it work just find.  

 

Now my software is ended, I want to program the EPCS to be allow to run the program without Eclipse. So, I change the Reset Vector (from SDRAM) to EPCS. I tried to lunch the software from Eclise (I have not programmed the EPCS at this time) and I got this error : 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=7936  

(0x4005000 is the EPCS first adress) 

 

I read the documentation, and some forums but I can not figure out what is wrong. 

 

Can you help me ? 

 

Ps : Sorry for my poor English, I am French 

 

Thank you 

Flandroid.
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2 Replies
Altera_Forum
Honored Contributor I
57 Views

There is probably an error in your link script. The EPCS controller contains a bootloader in ROM, which is at address 0x4005000. As it is ROM, it can't be rewritten, so you get this error. 

I don't know how Eclipse generates the BSP, but you should check the link sections for your project. All of them should be in the SDRAM. The only exception is .reset, which is IIRC hardware defined and will be the EPCS controller. The .entry section, on the other hand (I think it's called that), should be in SDRAM. The bootloader in the EPCS controller will copy the data from the EPCS to the SDRAM and jump to .entry
Altera_Forum
Honored Contributor I
57 Views

Pointing the reset vector to SRAM is unlikely to work (something else would need to write the code to SRAM before reset is removed). 

You are probably using the jtag debug to load your code - so the reset vector isn't used.
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