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Valued Contributor III
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Nios II Shadow Register Sets

Hello, 

 

in the NIOS II Processor instantiation -> Advanced Features -> Interrupt Controller: External -> Number of shadow register sets (0-63): 

 

Can someone tell me how many logic resouces ( RAM Blocks, Registers, etc ) are consumed 

for one shadow register set in the NIOS II instantiation ? 

 

Thank you for your reply.
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Valued Contributor III
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I think that any shadow registers sit in the same memory block(s) as the normal registers. 

Nothing else can use that memory block since the cpu uses both read ports and a write port every clock. 

So the shadow registers will just be using the unused space in that block until you exceed the size of the fpga's memory blocks. 

An M9K is 8k bytes, 32 registers use 128 bytes so 63 shadow sets will just fill an M9K block. 

Clearly there are a few extra latches to drive the high address lines, butthese won't amount to much.
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Valued Contributor III
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Hello dsl, 

 

thank you for your answer. 

 

You're right. 32 registers use 128 bytes. So 63 shadow register sets will need 8064 bytes. ( approx. 8K byte ) 

But a M9K memory block has onle 1K byte. ( 9126 bit ). 

 

If i'm not mistaken, 

up to 63 shadow register sets well need up to eight M9K bloks ( if they are implemented in Single Port Ram ) or up to 16 M9K blocks ( if they are implemented in Dual Port Ram ) 

 

Is this right ?
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Valued Contributor III
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I've only got a maths degree, I can't do sums :-) 

Dual porting memory doesn't take extra blocks. ISTR you can have one writer and two readers. 

In any case adding 7 shadow sets shouldn't increase the number of M9K blocks used.
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