I'm working on the Nios II with the device cyclone III, my flash EPCS64 memorycontains 2 FPGA images and 2 softwares. The 1st FPGA image (factory) address is 0, the 1st Nios software address is 0x2614E7, my 2nd FPGA image (application) address is 0x400000 and the 2nd Nios software address is 0x6614E7. When I damage voluntarily my 2nd Nios software I want to come back in my 1st FPGA image. Unfortunately I stay in my 2nd FPGA image but no software runs. The solution would be to enable the watchdog in 1st sof and after to boot on my 2nd FPGA image, and to disable it with my 2nd sof. If there is no 2nd sof present we come back to 1st FPGA image because watchdog wasn't disabled. Unfortunately when I try to read or to write in a Remote update register with my 2nd sof nothing happens I really don't understand maybe have I a problem with my bootloader modified -> From altera wiki (subject EPCS bootloader) http://www.alterawiki.com/wiki/file:asm_bootloader.zip (http://www.alterawiki.com/wiki/file:asm_bootloader.zip) I used the folder to generate my bootloader. I set :# define SOFTWARE_OFFSET 0x6614E7 # define EPCS_FLASH_CONTROLLER_0_BASE 0x08003800 -> defined in my sopc system I do a 'make' I've got my new bootloader.hex I place it my project , update it and then assemble my 2nd FPGA image. I'm in my second FPGA image but no software runs; so I did a 'make CODE_BASE=0', and then it works my second software runs well, but can't read or wirte in RU registers with my application code. Any help would appreciated, last step and my project is finished.
Hi Hulien_92,glad you figured it out, but where exactly in the attached document did you find that you have to reset the watchdog periodically? Would'n'T it be enough to just stop the watchdog?
page 17, 6-17 explains how to use the alt_alarm_start() which will call perdiocally the a function you've defined (like reset watchdog timer),unfortunately you can't stop the watchdog from your application software I thought it was possible but altera support told me it wasn't.
Hi,aha you meant the alt_alarm mechanism. I thought from your post, that you found the solution, that you have to reset the watchdog periodically in that data sheet But thanks anyway. But there have to be a way to stop that watchdog, that's not really a practical solution. BTW: On alt_alarm usage: The function which calls alt_alarm also increments the ntick counter, which you can read by alt_nticks(), this counter does not count up as long as the alt_alarm callback function is running. I had this problem when i tried to measure system time with this alt_ntick and saw it driftign away. So just keep that in mind.
Hi Julien,I am trying to use the same asm_sources as you did (http://www.alterawiki.com/wiki/file:asm_bootloader.zip). Remote update works for HW images but not for Nios. I have created a 1kB rom in the SOPC initialized with the my_boot_loader_standalone.hex file. I have mapped cpu reset vector to this rom but Nios does not boot. Is this method working for you ? Did you do something special ? I detailed every step in this post if you have a few minutes. http://www.alteraforum.com/forum/showthread.php?t=41648 Thanks in advance.
I used this method from altera wiki and it worked,but I did with another way, I modified boot_loader_epcs_bits_sii_siii_ciii.S directly from : D:\altera\10.1sp1\nios2eds\components\altera_nios2\boot_loader_sources. If you want in the following zip follow the instructions in info.txt to generate a new EPCS bootloader with the file .bat (maybe you'll have to change the path in this .bat with yours)
Thank you for you answer.It works !!! I had 2 problems: - I was using an onchip ROM instead of RAM to store the bootloader in SOPC - Then I have seen after reading back EPCS content that Nios binary file must be written without any byte modification unlike RBF files. So I have modified the ROM to RAM and the way I write nios file on EPCS and now everything is working. Now Nios can boot from a custom offset in EPCS and I can update binary file in EPCS !!