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Nios II core can't access peripheral in Arria 10 FPGA

LChen222
Beginner
295 Views

 

 

 

Hello, I run into peripheral access issue with developing Arria 10 embedded with Nios II. we implement peripheral with FPGA logic and attach it to Avalon bus. the periperal is mapped into registers in the address space such as 0x05000000. the problem is some register can't be read by Nios II core, but can be written by Nios II core. We tried to debug the problem with system console(Tcl console), eclipse. But they give different result

 

1 use Eclipse debug perspective, in the memory view, 0x05000000, modify the value such as 0x12345678, it will show 0x78787878 with some wrapping according to byte alignment

 

2 use Tcl console, master_32_read &jd 0x05000000, master_32_write &jd 0x05000000 can work as expected, the read value is the value which was written before. for instance, write 0x12345678, and read back 0x1234567

3 we use our code to use pointer function to access memory-mapped registers such as 0x05000000, it sometime show the correct value and sometime give wrong value

Did anyone face such problem? why Eclipse and Tcl console show different result? it seems contradictory, thanks in advance.

 

 

 

 

 

 

 

 

 

 

 

0 Kudos
2 Replies
Ahmed_H_Intel1
Employee
183 Views

Hi Lin,

Can you please share with me the screenshots of the NIOS II properties and connection?

Regards,

 

LChen222
Beginner
183 Views

 

The problem is resolved as we change wait cycle from 1 to 0 in avalon bus, thanks.

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