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Nios II delay calculation

Altera_Forum
Honored Contributor I
1,232 Views

hi i am a beginner in nios ii. i just wanted to know how to create a delay of 5microseconds using c code for nios ii processor. i intend to assert particular values on PIO for specific time intervals which would be captured by other FPGAs. Please if anybody could help, i would be grateful.

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Altera_Forum
Honored Contributor I
122 Views

I do something like this: 

 

// ****************************************************************************** // This is to allow very short delays for things like bit-banged timing // Assembler code is used to allow shorter loops // and to bypass compiler optimizations changing the timing of C code // This should generally not be called directly. A macro is included with fractional microsecond resolution void _short_delay(volatile int count) { // 'asm' notes: // Lines end with ';' // Embedded 'C' comments allowed (like /* comment here */, no double slashes) // Labels are the first non-white space, followed by a ':' // The compiler takes care of registers used when returning to standard C code asm(" ; ldw r2,0(sp) ; movi r3,-1 ; loop: ; add r2,r2,r3 ; bne r2,r3,loop ; "); } // a macro is defined in the header file for translating // delay based on count to one based on fractional micro-seconds i.e. //# define INSTRUCTIONS_PER_LOOP (3) //# define _uS(t) _short_delay((int)((t-0.3)*(ALT_CPU_FREQ/1000000/INSTRUCTIONS_PER_LOOP))  

 

Plain C can get optimized differently at different times. Using inline asm gets by this. The macro takes values from the BSP and adjusts for different clock frequencies. 

 

There is a partial adjustment for the call/return times, but the latency of SRAM is not included which can increase the loop time. Cache memory can lower this, but it often still affects the first loop until the instructions are in the cache. If you need to be exact, put this code it in closely coupled memory.
Altera_Forum
Honored Contributor I
122 Views

thanks fow this answer

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