I'm working on cyclone III with the EPCS64, in my Nios code C the time delay of erasing for one sector isdefined at 3 seconds to be sure of the erasing, I would like to know if there is a way to reduce this time of erasing in reading one of the epcs register for example ?
Assuming it is NOR flash, you repeatedly read the flash's status register until it indicates that the sector is written.I'd have thought that alt_epcs_flash_erase_block() already did that - IIRC you can't do any other flash cycles until the ease completes (it is a long time since I wrote NOR flash code). You should have the source for the flash functions - look at what they do.
I've something like that : // polling on the busy bit of the EPCS every 100 ms// while ((epcs_read_status_register(EPCS_CTRL_BASE_B+0x400) & 0x1) != 0x0) // OSTimeDly(OS_TICKS_PER_SEC/100); Don't know if I've to use it to look each 100 ms if I erased the sector, what is the value send back the alt_epcs_erase_block() ?!
FWIW if your board has two 16bit flash chips to generate a 32bit memory device, you must wait for both chips to signal that the erase (or write) has completed - that was the first bug I had to fix in the vendor supplied software for an evaluation board! (vendor and board will remain nameless!!).I don't beleive there is any reason to do any kind of delay between the reads of the status register. Once the erase/write is complete I think you then write to the device to terminate the erase/write - so this would have to be done inside the erase/write function. (It is over 10 years since I was doing this.) Just look at the source for alt_epcs_erase_block().
Ok, did it and just see that alt_epcs_erase_block() send back 0 when it's ok otherwise another value.So I did something like this while(alt_epcs_flash_erase_block(p_epcs_fd,epcs_addr)) OSTimeDly(OS_TICKS_PER_SEC); is it good to do this or am I completely wrong