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Nios II interface with pci-express

Honored Contributor II



I need to instantiate a NIOS II in an already designed FPGA using pci express communication. On the PC side, a driver is writing/reading registers in the FPGA through mapped memory. Now, I'd like to add a NIOS to the FPGA and be able to send commands ( Read / Write stuff ) from the PC. I have never instantiated a NIOS in an Altera chip so I'm wondering what are the possibilities to interface the NIOS with the pci express interface. I know there's the Avalon bus so maybe it's the key but I'm looking for some leads that I could read on.  


I thought about having the PC write in a custom IP / register through pci express. That write would trigger an interrupt on the NIOS ( or it could be pulled ). The NIOS would read what's in the register and execute what it needs to do. If the PC wants to read data, it would put a read command in a register. NIOS would see that read command and it could present the data to read on the pci express bus. I'm not sure how that's possible and if it's simple to implement. 


Thanks for any help!
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4 Replies
Honored Contributor II

I think this can be done  



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The data written into configuration registers of FPGA using PCIe should be given to NIOS  

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So One way of transferring the configuration register data to Nios is through PIO  


The same you mentioned by triggering an interrupt the config data can be read by NIOS  


Also the data can be send out of NIOS using the PIO  


This is a slow process but can be used as this is just for configuration
Honored Contributor II

There is a PCIe slave to Avalon master block that allows a single PCIe BAR to access multiple devices via the avalon bus. This is probably slightly slower than using a BAR for a single 'slave' but much more flexible. 

You might need to arrange the avalon slave addresses to reduce the address span - but we map a single 32MB BAR (16MB SDRAM + io). 


Be aware that all PCIe transfers are 64bit with 8 byte enables. The bus width adapter always generates two 32bit cycles, typically one has no byte enables asserted - if your slave assumes 32bit accesses it will get confused! 


You can then wite an avalon slave that can drive the Nios2 interrupt (and probably soft-rest) lines. No reason not to let the nios write as well and use a separate mask register, and maybe use 'write to set' and 'write to clear' registers to avoid read-modify-write cycles.... 


It will be simpler (but slower) if you do all the PCIe tranfers from the host. You'll need to get the nios to generate PCIe interrupts (we use a dedicated non-pcei interrupt), then have the host driver read a status regeister then the response (if available) - etc. 


If you need more than simple requests, use 'ring buffers' since they don't require the reader and writer to have write access to the same location, but allow mutiple requests be queued.
Honored Contributor II

Thanks for the info dsl. 


I'm not sure I grasped everything but let's see if I got at least part of it. 


The NIOS and the pci express would be linked by the avalon bus. Pci express requests could write in some registers, acting as a ring command buffer. For each writing, an interrupt could be generated on the NIOS to make it read the new data. An ACK could be written when the command has been processed somewhere in a register and the CPU could read that to know when the command has been processed. This wouldn't be the fastest approach but it could work. You brought the interrupt from the NIOS approach that looks interesting. Could the NIOS trigger an MSI interrupt through the pci ex to send back an ACK easily?  


I'm really new to that world of FPGA/soft cores like the NIOS and all so my vocabuly is probably inacurate... In the mean time, I'm trying to find app notes or technical design references about pci express and nios on altera's site to get familiair with all this...
Honored Contributor II

At a high level it isn't that much different to building a PCB with discrete components on it. 

The main difference is that the avalon 'bus' is slave arbitrated (ie there is a big mux in front of each slave), rather than being master arbitrated (with tri-state drivers). 

One advantage is that there is (probably) lots of simple logic available.