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Valued Contributor III
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Nios II max clock speed

Hi nios gurus, 

Does anyone know if the nios II is capable of running in the 123MHz range? I am using a nios I design with a cyclone dev kit currently and would like to step up to nios II. I'm not too worried about the overall performance, just clock speed. The reason for this is that i have built a small verilog module that is hooked up to the nios via the avalon bus and so am not allowed to feed it a faster clock speed without requiring the overall system to be picked up as well. Unless there is a way??? I don't know. Is there a way to run an external module with a separate clock speed and still be able to interact with the nios avalon bus?  

If this is not possible, then my options are limited... i like the nios and would hate to look for alternatives. 

 

thanx for any input on this problem. 

-Quan
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Valued Contributor III
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Re: Nios II max clock speed

If you want the fastest clock frequency and don't have high performance requirements, use the Nios II/e core since it is able 

to achieve over 180 MHz in Altera's fastest Stratix I devices (e.g. Stratix I, 1S40, C5 part). 

Even though you are using Cyclone and maybe a slower speed grade, this should give you enough headroom in Fmax. 

 

BTW, on the fastest Stratix I device, Nios II/f (highest performance) and Nios II/s (medium performance) can achieve up to 148 MHz for a small system with small caches. The hard limit on Stratix I devices is the hardware multiplier which runs up 

to 148 MHz. On fast Cyclone I devices, 125 MHz is about the fastest you'll see. 

The fastest Nios I achieves about 125 MHz on the fastest Stratix I devices so using Nios II will help you achieve Fmax goals. 

 

To get these frequencies, make sure you are using a recent version of Quartus, optimize for speed (instead of area), 

and turn on all the physical synthesis options.
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Valued Contributor III
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Re: Nios II max clock speed

Great thanx for the info James, 

Sounds like the niosI on a cyclone fpga can achieve what i am after. Theonly thing left I need to worry about is the interactions of the other components on the cyclone dev kits such as the sdram. On my system, the cache is not really that important right now so I can give a little bit back in that department. But the clock speed is very incouraging!! 

 

thanx again, 

-Quan
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Valued Contributor III
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Re: Nios II max clock speed

Here are some CPU IP core results...including new NIOSII core in the 3 different configurations: 

 

http://www.fpga.ch/ip_results.php (http://www.fpga.ch/ip_results.php

 

Interesting that optimizing between area/speed behaves totally unexpected in NIOSII core (o;
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Valued Contributor III
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Re: Nios II max clock speed

One additional piece of advice: The numbers James quotes for Nios apply to the CPU and interfaces to onchip memory, PIO, etc. If you add an SDRAM controller you'll probably see the f-max go down as that will be the critical path (I can't give you an exact quote for Cyclone, but our SDRAM controller tops out at around 105-110Mhz in Stratix (I)). 

 

If this does happen - and you need SDRAM in the same system as Nios - you'll need to design some logic that goes between your HDL and its Avalon interface to cross clock domains (a couple of synch. flops at the very least). The basic requirement is that user-definied logic imported to SOPC Builder have avalon port(s) which use the SOPC Builder system's clock... it is certainly legal to have an extra clock signal feeding your logic (of type "export" in the user-logic wizard).  

 

The cyclone chip you're using should have PLL circuitry that you can use to create two clocks of the speeds you need (take a look at the standard cyclone example design if you're not familiar with the PLLs - we use two of them to drive Nios, and send a phase shifted clock off to SDRAM).
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Valued Contributor III
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Re: Nios II max clock speed

Thanx for the input everyone. These are very useful tips. 

Jesse, the "export" signal is a very good idea. I will have to try that out. Currently my design seems very basic, I load in a bunch of data from compact flash card into sdram and then dma them continuously to an external device. This works okay since i can put in a 32 bit fifo to do some data buffering. But now they require to run at twice the data rate. The easiest choice I thought was to increase the clock speed. But now I see I can use the export port to send in a clock signal to drive the data out at twice the rate. The only problem i can see is that I require twice the amount of data in same amount of time. I guess I can increase the data width transfer size of the dma controllers to 64 bits or more into the same size fifo.  

Does this sound fair? I'll have to try it out.  

 

-Quan
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Valued Contributor III
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Re: Nios II max clock speed

Hi, 

 

I was trying to test this out... was able to run NIOSII upto 189MHz for Altera Cyclone II (DE2-70 dev board). Above this clock freq. the NIOS did not just respond.  

 

Hope this helps..  

 

 

Regards, 

BP
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Valued Contributor III
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Re: Nios II max clock speed

I suspect the speedup is primarily due to the toolchain improvements over the past 7.5 years! 

 

http://www.altera.com/literature/ds/ds_nios2_perf.pdf
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Valued Contributor III
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Re: Nios II max clock speed

 

--- Quote Start ---  

The reason for this is that i have built a small verilog module that is hooked up to the nios via the avalon bus and so am not allowed to feed it a faster clock speed without requiring the overall system to be picked up as well. Unless there is a way??? I don't know. Is there a way to run an external module with a separate clock speed and still be able to interact with the nios avalon bus? 

--- Quote End ---  

 

 

Use the Avalon MM Clock crossing bridge.
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