Nios II with enable Error-Correcting Code (ECC) (Qsys Design)

[Altera_Forum]

Hello Everybody ! 

 I'm trying to implement a Nios II Qsys Design with enable ECC. I'm using: 

• a fast Nios II (Gen2 Processor); 
• an On-Chip (RAM) memory with its ECC Parameter enable; 
• Others IP like JTAG, PIO, .... 

 ​ When I connect my data_master & instruction_master from my Nios II to my On-Chip Memory s1 port ( (Avalon Memory Mapped Slave), I have some errors:   [LIST=|INDENT=3] [*]error: unsaved.: signal data_master[8] and signal s1[39] must have the same symbol width; [*]error: unsaved.: signal instruction_master[8] and signal s1[39] must have the same symbol width; [*]error: unsaved.: signal data_master[8] and signal s1[39] must have the same symbol width; [*]error: unsaved.: signal instruction_master[8] and signal s1[39] must have the same symbol width; [*]error: unsaved.onchip_memory2_0.s1: data width must be of power of two and between 8 and 4096. [/LIST]  My On-Chip Memory is configured with a data width = 32. If I increase or decrease value of data width, I change error value from signal s1[xx].  For example, If I put data width = 64, my error value is now: error: unsaved.: signal instruction_master[8] and signal s1[72] must have the same symbol width  How I can update my instruction_master & data_maste port from my Nios II ?!  If anyone has any advice, it will be perfect :)  Thank a lot,  Remy

[Altera_Forum]

Nobody from Altera have an answer?

[Altera_Forum]

I assume that you checked the "Extend the data width to support ECC bits" or something like that depending on which version of Quartus. 

 The above option is only can be used when you have Tightly coupled instruction/data masters connected to it. If you want to connect to instruction_master and data_master, you need to uncheck the option.