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Altera_Forum
Honored Contributor I
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Nios II with on-chip Dual port ram between Nios and External DSP

Hello, 

 

I'd like to implement a dual port ram using on chip memory, with one side connected to the Avalon bus and other connected to an external DSP. Not sure where to get started; I can not seem to find a way to expose a DPRAM interface to external pins. Any suggestions as to where I can look? 

 

Thank you.
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20 Replies
Altera_Forum
Honored Contributor I
192 Views

What you probably want to do is create a Qsys component with an Avalon-MM Master, and conduit signals to connect to the DSP pins. 

 

Here's one similar thread: 

http://www.alteraforum.com/forum/showthread.php?t=3866
Altera_Forum
Honored Contributor I
192 Views

Thank you for your prompt response. 

 

I will try what you've suggested. Just for clarification (please correct me if I am wrong): 

 

1) I can create a dual port RAM component using Qsys; this DPRAM component will have two Avalon slave interfaces, s0, and s1.  

2) The first slave interface s0 will connect to the master port of the Nios II processor via the Avalon fabric, and the second slave port s1 will connect to the Avalon-MM master component as you've suggested. 

3) The newly created Avalon-MM component should be a 'dummy' that brings all of the master signals out via conduits? Then I can connect these to glue logic / pins as needed? 

 

I see that the dual port memory has an option for two clock inputs; I assume I need to use this since the external interface will be in a different clock domain (ie the external memory interface)? 

 

Best regards, 

Scott
Altera_Forum
Honored Contributor I
192 Views

You are mostly correct, except how "dummy" your module is depends on how (dis)similar your DSP memory controller is when compared to Avalon-MM. 

 

If you want to skip creating the Qsys component, you can simply "export" the second (s1) port of the dual port RAM. 

When you do that, in your top level module you will get a series of signals like this: 

 

unsaved u0 ( .onchip_memory2_0_s2_address (<connected-to-onchip_memory2_0_s2_address>), // onchip_memory2_0_s2.address .onchip_memory2_0_s2_chipselect (<connected-to-onchip_memory2_0_s2_chipselect>), // .chipselect .onchip_memory2_0_s2_clken (<connected-to-onchip_memory2_0_s2_clken>), // .clken .onchip_memory2_0_s2_readdata (<connected-to-onchip_memory2_0_s2_readdata>), // .readdata .onchip_memory2_0_s2_write (<connected-to-onchip_memory2_0_s2_write>), // .write .onchip_memory2_0_s2_writedata (<connected-to-onchip_memory2_0_s2_writedata>), // .writedata .onchip_memory2_0_s2_byteenable (<connected-to-onchip_memory2_0_s2_byteenable>), // .byteenable .onchip_memory2_0_clk2_clk (<connected-to-onchip_memory2_0_clk2_clk>), // onchip_memory2_0_clk2.clk .onchip_memory2_0_reset2_reset (<connected-to-onchip_memory2_0_reset2_reset>) // onchip_memory2_0_reset2.reset );  

 

which maybe is close enough for your system.
Altera_Forum
Honored Contributor I
192 Views

Hello, 

 

Thanks again, I was able to export the signals as suggested. 

 

I have a question regarding the second clock on the DPRAM; can this clock be asynchronous with the first clock that is connected to the Nios system clock? 

 

Best regards, 

Scott
Altera_Forum
Honored Contributor I
192 Views

 

--- Quote Start ---  

I have a question regarding the second clock on the DPRAM; can this clock be asynchronous with the first clock that is connected to the Nios system clock? 

 

--- Quote End ---  

 

 

Yes. The two ports are independent.
Altera_Forum
Honored Contributor I
192 Views

If the clocks are different you'll get 'random' data if a read and write to the same location happen 'at the same time' (probably with any overlap between the two clock cycles). 

You'll need to ensure that this doesn't happen, or that the read values don't matter.
Altera_Forum
Honored Contributor I
192 Views

Hello, 

 

I've attached a screen shot showing the Qsys configuration and schematic; if possible, can you perhaps confirm if what I have shown is what was suggested? 

 

Thank you and best regards, 

Scott
Altera_Forum
Honored Contributor I
192 Views

 

--- Quote Start ---  

Hello, 

 

I've attached a screen shot showing the Qsys configuration and schematic; if possible, can you perhaps confirm if what I have shown is what was suggested? 

 

Thank you and best regards, 

Scott 

--- Quote End ---  

 

Yes, its correct! 

Did You manage to connect External DSP to the exported second (s1) port of the dual port RAM? 

 

If Yes , the please answer: 

1). why Write signal is present, but the Read signal is missing on the exported second (s1) port of the dual port RAM? 

2). Is Write really is WriteEnable? 

3). how to use clken ( clock enable ) on the exported second (s1) port of the dual port RAM?
Altera_Forum
Honored Contributor I
192 Views

You can't use clken in dual port mode with a single clock (and you must use single clock mode to get OLD_DATA - which you probably want). 

There is an alternate address hold (I think) signal which has basiaclly the same effect.
Altera_Forum
Honored Contributor I
192 Views

Ok - if you need dual clock then you have to live with random data during concurrent read/write of the same address - note the you can get some bits of the old data and some of the new. 

M9K don't have a 'read' signal, they do reads every cycle. You can use the clken to stop this - and keep the output data constant even though the address has changed.
Altera_Forum
Honored Contributor I
192 Views

 

--- Quote Start ---  

Ok - if you need dual clock then you have to live with random data during concurrent read/write of the same address - note the you can get some bits of the old data and some of the new. 

M9K don't have a 'read' signal, they do reads every cycle. You can use the clken to stop this - and keep the output data constant even though the address has changed. 

--- Quote End ---  

 

OK, thank You for the answer about Read. 

What then could be the solution to have a real dual-port memory ( without the problems during concurrent read/write of the same address ) with one port being controlled by NIOS II and the other by custom logic?
Altera_Forum
Honored Contributor I
192 Views

You have to use a single clock and then enable OLD_DATA. 

And still not do two writes to the same location. 

Note that feeding the same clock to both clock inputs doesn't count - the M9K has to be configured with a single clock input. 

If the Nios cpu (or other avalon master) is using a different clock then a clock crossing bridge will be added. 

 

I mostly know about this because we had issues with the sopc builder silently ignoring OLD_DATA for M9K dual ported between the avalon bus and tightly coupled memory. 

IMHO internal memory should always be tightly coupled to the nios cpu (unless you need the 2nd port for something else).
Altera_Forum
Honored Contributor I
192 Views

 

--- Quote Start ---  

 

If the Nios cpu (or other avalon master) is using a different clock then a clock crossing bridge will be added. 

--- Quote End ---  

 

Do You mean, that QSYS will add it automaticaly or should I add it manually? 

 

--- Quote Start ---  

 

IMHO internal memory should always be tightly coupled to the nios cpu (unless you need the 2nd port for something else). 

--- Quote End ---  

 

Do You mean, that if 2nd port is controlled by my custom logic, then internal memory should not nessecary be tightly coupled to the nios cpu?
Altera_Forum
Honored Contributor I
192 Views

How does this scheme change if you instantiate a dpram outside of qsys, but wish to access it from nios (instruction and data)? The megafunction dp ram has just a few signals for each port (address, output read data, input write data, write enable, and clock), but the memory controllers in qsys are all s/dram based, with ras, cas, etc... 

 

Incidentally, one of the reasons I'm looking at instantiating the memory OUTSIDE of qsys, is because quartus seems to have trouble fitting the design when I specify too large of a memory block in qsys. Interestingly, 15k won't fit, but 14k will.. and the fit summary shows only 25% memory utilization (and 65% logic)! So obviously, the 1k isn't causing it to run out of memory, it must be something else. 

 

Outside of qsys I can instantiate a 17k dpram (or much bigger) and it synthesizes fine, thus I'd like the nios to execute from this "external" memory.
Altera_Forum
Honored Contributor I
192 Views

I don't think the scheme changes at all; it is the same basic concept just applied slightly differently. 

 

e.g. insert an Avalon-MM Pipeline Bridge, connect it's slave port to your NIOS, and export it's Master port as a conduit. In your toplevel, connect the master conduit pins to your dual port RAM.
Altera_Forum
Honored Contributor I
192 Views

The 'memory utilisation' of 25% means that you are using 25% of the memory bits, not 25% of the memory blocks. 

If something is using a small number of address or data bits in a memory block then the utilisation will be reported as low even though the other bits can't be used.
Altera_Forum
Honored Contributor I
192 Views

 

--- Quote Start ---  

Yes, its correct! 

Did You manage to connect External DSP to the exported second (s1) port of the dual port RAM? 

 

If Yes , the please answer: 

1). why Write signal is present, but the Read signal is missing on the exported second (s1) port of the dual port RAM? 

2). Is Write really is WriteEnable? 

3). how to use clken ( clock enable ) on the exported second (s1) port of the dual port RAM? 

--- Quote End ---  

 

 

Did you get an answer to this? I have the same question. Since there is no read signal exported the write must be a write/read_n or write high read low level? Is clken or chipselect used as a data strobe? Are all signals active high? clken, chipselect, write? byteenable is active high so if you specify byteenable as all ones 4'b1111 for 4 byte 32 bit interface you are writing all 32 bits in one write cycle.
Altera_Forum
Honored Contributor I
192 Views

Reads happen every clock without an explicit enable (other than clken). 

clken stops the address being latched so has the effect of holding the previous data-out even though the address is no longer present.
Altera_Forum
Honored Contributor I
192 Views

Thank you. 1) Is clken active high? 2) Is chipselect active high? 3) Is reset for the onchip mem s2 active low?

Altera_Forum
Honored Contributor I
37 Views

I just answered 3) in my last post false so reset is active high as are clken and chipselect.

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