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12452 Discussions

Nios - Problem to Read from DDR3

Altera_Forum
Honored Contributor II
1,524 Views

Hello everyone, 

 

I am working with the Arria II GX FPGA along with Quartus 10.1. 

 

I am trying to write data into an external ddr3 memory (2 gbits) using the altmemphy ddr3 memory controllers instantiated in the sopc builder and read back the same from the nios processor. However, I have a lot of trouble in Reading back the data! :confused: 

 

Initially, I had configured the DDR3 memory as 128M x 16, with 16 data lines (DQ). With this configuration, when I tried to read 4 bytes, I always got only the first 2 bytes. The last 2 bytes were garbage values. 

 

Later, I observed that the Altera Evaluation Board reference design has 8 data lines and so modified my DDR3 configuration (just a try) to - 256M x 8, with 8 data lines (DQ). Now, when I try to read 4 bytes, I receive the first 3 bytes and the last byte always has garbage values! :rolleyes: 

 

As I am not a DDR3 expert, would be great if anyone could shed light on this and help me figure out the problem. Is it a timing issue?
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7 Replies
Altera_Forum
Honored Contributor II
104 Views

Hi, 

 

This can be caused by the cache of the Nios. 

Try to read uncached data (I thought by reading at the address that you read now but with MSB set to '1').
Altera_Forum
Honored Contributor II
104 Views

Hey, 

 

I have tried your suggestion, but, this doesn't seem to be the problem. Any other ideas, suggestions...?
Altera_Forum
Honored Contributor II
104 Views

Do you actually know if it the read or write that fails? 

Quite possibly the timings are wrong and some of the data is being latched before it is valid (or after it has become invalid).
Altera_Forum
Honored Contributor II
104 Views

Hello dsl, 

 

Although I am not 100% sure, I strongly suspect it to be a "read" error.  

 

Any hints as to which ddr3 timing parameters I may want to look into to get around this problem...?
Altera_Forum
Honored Contributor II
104 Views

If this is a custom board (i.e. not a dev kit) then I recommend finding the datasheet for your particular memory device if it's not already listed in the memory presets. If you randomly picked some DDR3-SDRAM preset that doesn't match your own memory then you won't have much of a chance getting it to work without changing the timings manually. 

 

Last but not least is your design meeting timing in Timequest? If not then that could be your problem.
Altera_Forum
Honored Contributor II
104 Views

It is a custom board and I am using a custom preset for the DDR3 that is used. And yes, Timequest seems to be happy! Still, no luck!

Altera_Forum
Honored Contributor II
104 Views

I recommend creating a test hardware project that contains a Nios II 'f' core, a DMA called "dma", JTAG UART, 64kB on-chip memory, and the SDRAM controller. Run the test program called "memtest" from the on-chip memory and use it to test your SDRAM to make sure it is operating correctly. You'll need to connect the CPU data master and both DMA masters to the SDRAM controller for this test to work properly.

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