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Honored Contributor I
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Nios Read Data Never Appears on Nios Read Bus

In our Arria 10 design, we have a custom IP block for the Nios data and instruction memory. The underlying memory consists of two 4Kx32 memory blocks, shared with other 64-bit processing elements in the system. The Nios fetches and writes data, but obviously 32 bits at a time. We can successfully write to the memory but have a problem reading from memory. 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12767&stc=1  

 

As a test, we can successfully read and write using a Qsys onchip memory component. The primary difference is that the onchip memory component doesn't have the ability toadd wait-states (other than the initial wait-state issued by the adapter). Our IP potentially issues wait-states if there is an arbitration conflict between the various memory read and write ports. Also, fundamentally, there's a LOT more going on within our custom IP block. 

 

 

The problem we see is that read data never actually seems to make its way back to the Nios processor through all the Qsys-generated network logic. Here’s a waveform diagram of what we’ve captured using Signal Tap (a PDF is attached in case that’s easier to read). 

 

 

Fundamentally, we can see that Nios successfully writes to memory (not shown in this diagram) and it appears that it also successfully reads from our custom IP memory block. However, as shown in Step 10 in the Signal Tap waverform, the data never actually appears on the Nios processor read bus! We're at a loss on what to try next. Everything seems to be properly aligned but somehow the data is lost in the Qsys-generated logic before it reaches the Nios processor. 

 

 

Any and all relevant comments and suggestions are strongly welcomed! 

 

 

Family: Arria 10 

Nios: Nios II/f 

Qsys Pro (Beta) 16.0.2 Build 222 

Qsys Prime Version 16.0.2 Build 222 07/20/2016 SJ Pro Edition
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