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Nios communicate with external dsp(dual port ram inside)

Altera_Forum
Honored Contributor II
787 Views

Recently I want to use Nios communicate with external device. 

The device is a RT-Ethernet chip,which have a ARM and dpram in ti.So FPGA and ARM will access the shared dpram. 

I don't know what should I add in Nios to implement this function. I'm not sure that 'avalon tristate bridge' can be used.  

 

Thank you very much!
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Altera_Forum
Honored Contributor II
107 Views

I have write an interface for nios and external ram. 

Could someone give me some instructions?Thanks a lot! 

 

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.std_logic_unsigned.all; 

 

entity TPS_Bridge is  

port ( 

-- global signals (clock and reset) 

clk : in STD_LOGIC; 

resetn : in STD_LOGIC; 

 

-- Avalon-MM slave generic signals 

-- note that there is no address as this component 

-- only has 1 read and write register 

chipselect : in STD_LOGIC; 

address : in STD_LOGIC_VECTOR (15 DOWNTO 0); 

byteenable : in STD_LOGIC_VECTOR(1 downto 0); 

 

-- Avalon write interface 

avalon_writen : in STD_LOGIC; 

writedata : in STD_LOGIC_VECTOR (15 downto 0); 

waitrequest : out STD_LOGIC; 

 

-- Avalon read interface 

avalon_readn : in STD_LOGIC; 

readdata : out STD_LOGIC_VECTOR (15 downto 0); 

 

--TPS-1 DPRAM interface 

 

TPS_data : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0); 

TPS_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); 

TPS_CS : OUT STD_LOGIC; 

 

TPS_RD : OUT STD_LOGIC; 

TPS_WR : OUT STD_LOGIC; 

TPS_RDY : IN STD_LOGIC; 

TPS_BYTE_SEL_LOW : OUT STD_LOGIC; 

TPS_BYTE_SEL_HIGH : OUT STD_LOGIC 

); 

end entity TPS_Bridge; 

 

architecture InterfaceLogic of TPS_Bridge is 

begin 

TPS_addr <= address(15 DOWNTO 0); 

TPS_RD <= avalon_readn; 

TPS_WR <= avalon_writen and byteenable(0) and byteenable(1); 

TPS_CS <= chipselect; 

TPS_BYTE_SEL_LOW <= byteenable(0); 

TPS_BYTE_SEL_HIGH <= byteenable(1); 

waitrequest <= TPS_RDY; 

 

tristate_control: process(TPS_RDY,avalon_writen,chipselect,avalon_readn) 

begin  

if (avalon_writen = '0' and chipselect = '0' and TPS_RDY = '0')then 

TPS_data(15 DOWNTO 0) <= writedata(15 DOWNTO 0); 

elsif(avalon_readn = '0' and chipselect = '0' and TPS_RDY = '0')then 

readdata(15 DOWNTO 0) <= TPS_data(15 DOWNTO 0); 

end if; 

end process tristate_control; 

 

end architecture InterfaceLogic;
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