Nios locks up with data cache bursts enabled

[Altera_Forum]

When I use the "enable bursts" feature on the Nios II data cache, my processor is locking up on an IORD instruction. 

 I can reproduce this problem using a simple setup consisting on a Nios II/f, with an 8k data cache. The CPU instructions are stored in an internal RAM, and the CPU's data_master port is connected to an SDRAM controller. I also have a simple DMA module with a read and write port connected to the SDRAM controller.  The Nios is running a simple program which reads from and writes to buffers stored in SDRAM. At the same time, the DMA module is copying data from one SDRAM location to another. The program runs without a problem when I uncheck the "enable bursts" in the cache tab of the Nios in SOPC. But when I recompile with "enable bursts" checked, the program runs for a little while and then hangs on an IORD instruction. If I step through the the disassembly, the Nios locks up after running a LDWIO instruction.  Anyone have any experience enabling burst reads and writes in the Nios II data cache?

[Altera_Forum]

Update:  

Using SignalTap, I can see that the reason the Nios is locking up is because it is waiting indefinitely for the Avalon read instruction to complete. The Nios data_master port is issuing a read, but the wait_request signal is never going low. On the slave side, however, the Avalon read signal is never going high. So something in the auto-generated interconnect appears to be indefinitely stalling the read.

[Altera_Forum]

I tried the same design in QSys and the Nios cache bursts are working. I guess this is a SOPC interconnect bug that has been fixed in QSys.

[Altera_Forum]

I'd bet on a timing error - your system probably isn't correctly constrained.

[Altera_Forum]

I have this problem too using Qsys. Anybody find a solution for this?? Was it a timing problem?

[Altera_Forum]

OK. Another poster mentioned that he had problems with 8K data cache so I tried using only the default 2k and it worked.