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12453 Discussions

Nios/qsys address map (beginner)

Altera_Forum
Honored Contributor II
1,240 Views

Hello everyone, 

 

As title states, I'm new to alteras Qsys, Nios and related tools. I started with alteras tutorials, creating a simple system with Nios2, pio etc. 

 

Then I tried a simple software - writing/reading to/from IO locations(peripherals) like PIO and RAM. So far so good, but then I tried to write/read to a seemingly unmapped locations.. and I got back what I had written.. Here's the address map from Qsys: 

 

http://www.bildites.lv/images/hngxsps4dvklrlwwcfjg.png  

 

So addresses from like 0xf up to 0x8000 should be unmapped, right? What am I missing here? 

 

Thanks in advance, 

 

Vents
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
146 Views

The picture link that you posted is not showing up

Altera_Forum
Honored Contributor II
146 Views

I had a similar thing happen with a project. When I asked a real EE, he said that I was reading back the residual value on the bus. Since there weren't any pull up/down resisters in the FPGA the value of the internal signals takes some time to go back to the unexcited state. When I added a delay before reading back it was random again.

Altera_Forum
Honored Contributor II
146 Views

Hmm, i don't know why you can't see the image. I uploaded it on google drive, you should be able to see it or dl it here: 

 

https://docs.google.com/file/d/0b8zjwv2o45ourjfim3rydmtxsvu/edit 

 

I tried to add delay, but still got the same results. Also, when writing to these seemingly unmapped locations, sometimes the program starts acting weird in the debug mode like skipping to the end or crashing the debug mode all together :|
Altera_Forum
Honored Contributor II
146 Views

so what are actual write/read commands that you are sending?

Altera_Forum
Honored Contributor II
146 Views

Are your test writes and reads bypassing the data cache? 

If not then you are just testing the cache!
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