Hi guys,I have generated 512 words dual port memory with 16 bit wide through Qsys. When am simply reading from the memory, the counter data am missing data in between. I don't do any activity other than reading, even then am missing data. Whenever FPGA writes data to dual port memory, it will generate one pio trigger, after receiving trigger nios will read from the memory. Counter data is updated at 48 mhz, nios is running at 200 mhz. Please help me to solve the above problem
Dump the disassembly of your reading loop and then count the clocks required for each instruction. At roughly (5) clocks per iteration, you don't have a very large margin for error or inefficient code.
Is the trigger done via interrupt? Nios ISR is not that fast and surely can't be done within a 4-5 cycles (assuming that the ratio is 200/48 Mhz). Also is this e-core?
Himikedsouze and ted thanks for your time, I think i have not conveyed properly. The memory value is updated at every 48 MHz, after updating the all 512 locations and time elapsed is 640usec (if these 2 conditions are met) FPGA (Stratix V) will give PIO Trigger. Now at NIOS-II side ISR is implemented to read the all 512 locations. What i feel is time available to read the contents is worst case 640usec. As NIOS-II is running at 200MHz i should not miss any data. How i am checking data is missed, out of 512 locations one location is sequence number. Out of 100 times i do this operation one or 2 times i am missing data.I am simply copying the present data and comparing the sequence number of the previous buffer data, ideally it should be always one. But sometimes value is other than one, this is happening once in hundred times. Regards, Siva
Is the Nios CPU doing anything else? If you have other ISRs that get called (the system timer for example) it could cause some delays in processing our PIO interrupt some times.