Hello everybody;I made my custom logic that accepts 2 inputs each of 128 bits wide and produces 128 bits reault, is this any way to integrate my logic with Nios2 and deal with it by a custom instruction.
If the several clocks necessary is OK, then yes you can use a multi-cycle custom instruction that accesses the NIOS register file to read the two 128-bit inputs and then write the 128-bit output. See page 1-9 of http://www.altera.com/literature/ug/ug_nios2_custom_instruction.pdfHowever, if you wish to achieve relatively high throughput, you would be better off putting your accelerator in a custom IP block with an Avalon-MM Slave interface for control and one or more Avalon-MM Master ports to read/write your data directly from memory.
Thank you Mr ted for your attension;I have already defined my avalon memory mapped slave component with Qsys, but how can I access it through eclipse. Thanks.
For a custom instruction you'd have to use mutiple opcodes to write the 128bit values and then multiple opcodes to retrieve the result.It could all be done with a single clocked (not combinatorial) custom instruction opcode. If 'readrc' is zero use the 5 bit C value to select where to save the 32bit rA and rB values. If 'readrc' is one use the A field to determine which result to return. (Actually you can look at the writera bit and the 32bit A value as well, and all the B ones.) I didn't ever look to see if the writera/writerb bits have any effect on the cpu logic. I strongly suspect that the pipeline stall (for an earlier 'late result') always happens. All other instructions stall on the A field, a B field stall is needed if the low two bits of the opcode differ. It seems highly unlikely that the custom opcode bits get fed in to that logic, it is even possible that it applies to jmpi and call instructions.