Hi everybody. I'm trying to transmit array from onchip memory through DMA to on chip FIFO and then read data from FIFO to another array. Parameters are as follows: fifo - depth=1024, dual clock mode, MM write/read interfaces,data width = 8, dma - data transfer fifo depth = 32, burst transfers are disabled. If I use burst transfers option dma transaction doesn't finish, without burst transfers option data transfer occurs, but the output array differs from original one (some bytes are the same, but other bytes are 0x00). Where could the problem be?
With bursting enabled you are resticted to the transfer length being equal to the burst length, since you are using on-chip RAMs and FIFOs I don't recommend bursting. Which data width settings did you enable in the DMA? You are using 8-bit transfers but if you only enabled the 8-bit hardware you might need to enable 16 and 32-bit hardware as well (and just not use it that wide). I would explain that recommendation but I can't remember for the life of me what bug that worked around (and whether or not it was ever fixed).Another bug you might be running into is in the driver. A long time ago I remember hitting a bug where if you logically OR'ed a bunch of flags together only one would stick. The workaround was to call the ioctl with one flag at a time. In your case you are probably setting the data width to 8-bit and setting RCON bit when reading from the FIFO (so that the address doesn't increment). In that case you'll need to call ioctl twice, once for the 8-bit flag and again for the RCON flag. If you end up hitting a wall with that DMA you might have an easier time using the DMA engine I created: http://www.alterawiki.com/wiki/modular_sgdma
Thank you for the answer, BadOmen. All data widths for DMA are enabled (byte,halfword,word...). I'll try using two ioct commands but it seems RCON is OK. I'm working on ethernet interface based on wiz820io module, so I have to reorganize received bytes that form TCP packets into a bit stream. I've also considered using DMA and external fifo, but byte duaration on DMA output varies from 1 clk period to 3 clk periods, so it's impossible to write data correctly into fifo. As regards SGDMA I don't think I need such complicated component cause I'm only going to realize 100Mbps Ethernet and I'm trying to be economical with FPGA resources.