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12409 Discussions

Nios2 and external Microcontroller together access a SDRAM

Honored Contributor II

Hi all, 


My system consists of a microcontroller (TI Concerto Cortex M3) 

and a FPGA (altera cyclon IV E) and a SDRAM. 

The microcontroller connects only with FPGA(Address / data / control signals). The SDRAM is connected directly with the FPGA. 


I plan to: 

A portion of the SDRAM is reserved for Nios2 (Data and 

Instructionmemory), the remainder of the SDRAM 

is for the Microcontroller (Concerto). 


My question is, how can i achieve this? 


In this case i have 2 Avalon MM Masters, Nios2 (higher priority) and the external Microcontroller (lower priority), both access the SDRAM over SDRAM Controller IP. Which solution is the best for me? 


Thanks in advance! 

0 Kudos
2 Replies
Honored Contributor II

Leave the bus arbitration for the subsystem itself - it will do it automatically. However I hope You don't need speed, since sharing a memory bus slows down the system because of many wait requests...

Honored Contributor II

Hi Socrates, 


many thanks for your reply!:-) 


My Nios2 runs at 75Mhz, but this is not fixed. 

Is there an other solution besides the Avalon MM Master for me? Cant i tell the Qsys, let Nios2 higher priority, so that the Microcontroller must wait until ther Nios2 is done with SDR-SDRAM? 


thanks in advance! 


ps. sorry for my english!:(