Re: Nios2/e Remote Upgrade in MAX10

Altera_Forum · ‎10-17-2017

Hi,

I am trying to implement a remote FPGA upgrade configuration using a MAX10 FPGA with NiosII/e. Nios is running from UFM of max10 (Not enough OCRAM left for nios). and small ocram for ISRs. Nios instruction masters keeps the on-chip flash IP always in read-busy. Therefore, I can't issue any command to erase or write the CFM of device for remote update.

How can i stop instruction master from accessing flash. Why it does so even when executing exceptions?

What i tried so far:

- Added OCRAM for exception vector and added CFM ersae and write code in ISR -- Did'nt work

- Ofcourse, running nios from OCRAM worked. But I cant run it in actual project due to limited resources.

Looking forward to any suggestions.

Altera_Forum · ‎12-26-2017

--- Quote Start ---

Hi,

I am trying to implement a remote FPGA upgrade configuration using a MAX10 FPGA with NiosII/e. Nios is running from UFM of max10 (Not enough OCRAM left for nios). and small ocram for ISRs. Nios instruction masters keeps the on-chip flash IP always in read-busy. Therefore, I can't issue any command to erase or write the CFM of device for remote update.

How can i stop instruction master from accessing flash. Why it does so even when executing exceptions?

What i tried so far:

- Added OCRAM for exception vector and added CFM ersae and write code in ISR -- Did'nt work

- Ofcourse, running nios from OCRAM worked. But I cant run it in actual project due to limited resources.

Looking forward to any suggestions.

--- Quote End ---

Hello,

I have the exact same problem.

If you find a solution please post.

David

Altera_Forum · ‎12-27-2017

Hi,

I solved by creating a small OCRAM and a seperate linker section for this OCRAM. Flash functions are placed on this OCRAM, whereas the rest of the code executes normally from the flash.

Altera_Forum · ‎12-27-2017

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Hi,

I solved by creating a small OCRAM and a seperate linker section for this OCRAM. Flash functions are placed on this OCRAM, whereas the rest of the code executes normally from the flash.

--- Quote End ---

That's great.

Unfortunately I do not have the knowledge to do that.

Could you show me how you directed the linker to place only these certain sections of code in OCRAM (and which sections exactly).

Are you using

Much appreciated.

David

Altera_Forum · ‎12-27-2017

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That's great.

Unfortunately I do not have the knowledge to do that.

Could you show me how you directed the linker to place only these certain sections of code in OCRAM (and which sections exactly).

Are you using

Much appreciated.

David

--- Quote End ---

Sure. Here are the steps I took.

1. Edit BSP with an ocram private(you can use any name) sector.

https://www.alteraforum.com/forum/attachment.php?attachmentid=14599

2. You need to edit the linker script of NIOS. For example:


    Rest of the script...
    .private : AT ( LOADADDR (.text) + SIZEOF (.text) )
    {
        PROVIDE (_alt_partition_private_start = ABSOLUTE(.));
        *(.private .private.*)
        . = ALIGN(4);
        PROVIDE (_alt_partition_private_end = ABSOLUTE(.));
    } > ocram_private
    
    PROVIDE (_alt_partition_private_load_addr = LOADADDR(.private));
    
    .rodata : AT ( LOADADDR (.private) + SIZEOF (.private) )
    {
  
  Rest of the script...

3. In C code, instruct linker to put function on private section, e.g.:

__attribute__ ((section(".private"))) extern void write_page( )

4. Edit bootloader(alt_load.c) to load that section memory, already a function available, just call:

ALT_LOAD_SECTION_BY_NAME(private);

Good Luck