Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12455 Discussions

Nios2 wont give data for 8 clock

Altera_Forum
Honored Contributor II
731 Views

Hello friends, 

My software on nios SBT put high on PIO_STRT_OUT pin IOWR_ALTERA_AVALON_PIO_DATA(PIO_STRT_OUT_BASE,HIGH), 

and it reflect (STRT) on output also (attached printscreen), this start out trigger a 8 bit parallel to serial (P2S) converter external to nios processor (attached printscreen), and then this P2S generate a load pulse (LD) which feedback to processor, which tells processor that give a one byte of data (DATA[7..0]) stored in an array,  

 

Problem: output DATA[7..0] first word 164 is available for jut 5 and ½ clock period not for 8 clock period like rest of the data is available for 8 clock as load pulse arrive every 8th clock pulse. 

 

Regards 

kaushal
0 Kudos
0 Replies
Reply