Re: NiosII SPI Core problem

Altera_Forum · ‎08-16-2011

Hi, all

i use a SPI core in my nios system.

when i used the function "alt_avalon_spi_command()" to sent a "who am i" command to the peripheral, it received no data. so i use signalTap to debug.

here's the data i got

http://ww1.sinaimg.cn/large/4abedc10gw1dk7o6m3q7ej.jpg

my questions:

1)MISO has received the data sent back by peripheral, why rx_holding_reg and shift_reg received nothing?

2)is there anything wrong in my code?

int main()
{
    alt_u8 temp;
    alt_u8 wdata = 0x80 | WHO_AM_I;
        
        if(alt_avalon_spi_command(
                                SPI_L3G4200_BASE,0,
                                1,&wdata,
                                1,&temp,
                                0)==0)
            printf("fail\n");
        else
        {
            printf("%d\n",(int)temp);
        }
    }

thanks

Altera_Forum · ‎08-16-2011

It's been a long time since I have used that core but I recommend looking at the control and status registers of the SPI core to make sure the TX hasn't overflowed or the RX hasn't underflowed. I forget the behavior but in those two cases the SPI component either stops moving data or it just loops the data back.... or something.... I forget.

Altera_Forum · ‎08-17-2011

TAT... i make it.

when i add a NOT gate at MISO, it works.it seems that Nios cannot catch the signal starts with "1".

Altera_Forum · ‎08-17-2011

Try increasing the delay parameter of the SPI core so that there is a bit of delay between the SS_N deassertion and sclk. One sclk of delay should hopefully do the trick.

Altera_Forum · ‎01-09-2012

Hi everyone!

I'm also using an SPI core to connect my peripheral to nios and I also send "who_am_i" command, but I'm experiencing some difficulties. When I send data using altera_avalon_spi_command(), here are the signals from SignalTap Logic Analyzer (SCLK, SS_n, MOSI, MISO):

https://www.alteraforum.com/forum/attachment.php?attachmentid=5300

My SPI is configured as master, SCLK=10MHz, Data Register width = 8, Clock polarity = 1, Clock phase = 1. I can see that in q3ccn's picture spi clock exists as long as SS_n signal is deasserted which doesn't happen in my case. So, I suppose that in the first clock cycle in my picture, the data (0x8F) is sent over MOSI line, but what happens in the other cycle? Why is there such a big period between these cycles? Is it possible that data is sent again in that second cycle or the received data is sampled from the MISO line?

When I configure MISO pin as an input pin in quartus, should I enable pull-up resistor or it is not necessary?

Thanks for any help.